Quad-Serial Configuration (EPCQ) Devices Datasheet

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ID 683078
Date 1/23/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quad-Serial Configuration (EPCQ) Devices Datasheet
1. Quad-Serial Configuration (EPCQ) Devices Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Memory Array Organization 1.5. Memory Operations 1.6. Registers 1.7. Summary of Operation Codes 1.8. Power Mode 1.9. Timing Information 1.10. Programming and Configuration File Support 1.11. Pin Information 1.12. Device Package and Ordering Code 1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. ICC Supply Current 1.3.5. Capacitance
1.4. Memory Array Organization x
1.4.1. Address Range for EPCQ16 1.4.2. Address Range for EPCQ32 1.4.3. Address Range for EPCQ64 1.4.4. Address Range for EPCQ128 1.4.5. Address Range for EPCQ256 1.4.6. Address Range for EPCQ512/A
1.5. Memory Operations x
1.5.1. Timing Requirements 1.5.2. Addressing Mode
1.6. Registers x
1.6.1. Status Register 1.6.2. Flag Status Register 1.6.3. Non-Volatile Configuration Register
1.6.1. Status Register x
1.6.1.1. Read Status Register Operation (05h) 1.6.1.2. Write Status Register Operation (01h)
1.6.1.1. Read Status Register Operation (05h) x
1.6.1.1.1. Block Protection Bits in EPCQ16 when TB Bit is Set to 0 1.6.1.1.2. Block Protection Bits in EPCQ16 when TB Bit is Set to 1 1.6.1.1.3. Block Protection Bits in EPCQ32 when TB Bit is Set to 0 1.6.1.1.4. Block Protection Bits in EPCQ32 when TB Bit is Set to 1 1.6.1.1.5. Block Protection Bits in EPCQ64 when TB Bit is Set to 0 1.6.1.1.6. Block Protection Bits in EPCQ64 when TB Bit is Set to 1 1.6.1.1.7. Block Protection Bits in EPCQ128 when TB Bit is Set to 0 1.6.1.1.8. Block Protection Bits in EPCQ128 when TB Bit is Set to 1 1.6.1.1.9. Block Protection Bits in EPCQ256 when TB Bit is Set to 0 1.6.1.1.10. Block Protection Bits in EPCQ256 when TB Bit is Set to 1 1.6.1.1.11. Block Protection Bits in EPCQ512/A when TB is Set to 0 1.6.1.1.12. Block Protection Bits in EPCQ512/A when TB is Set to 1
1.6.2. Flag Status Register x
1.6.2.1. Read Flag Status Register Operation(70h)
1.6.3. Non-Volatile Configuration Register x
1.6.3.1. Read Non-Volatile Configuration Register Operation (B5h) 1.6.3.2. Write Non-Volatile Configuration Register Operation (B1h)
1.7. Summary of Operation Codes x
1.7.1. 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) 1.7.2. Write Enable Operation (06h) 1.7.3. Write Disable Operation (04h) 1.7.4. Read Bytes Operation (03h) 1.7.5. Fast Read Operation (0Bh) 1.7.6. Extended Dual Input Fast Read Operation (BBh) 1.7.7. Extended Quad Input Fast Read Operation (EBh) 1.7.8. Read Device Identification Operation (9Fh) 1.7.9. Write Bytes Operation (02h) 1.7.10. Extended Dual Input Fast Write Bytes Operation (D2h) 1.7.11. Extended Quad Input Fast Write Bytes Operation (12h or 38h) 1.7.12. Erase Bulk Operation (C7h) 1.7.13. Erase Sector Operation (D8h) 1.7.14. Erase Subsector Operation
1.9. Timing Information x
1.9.1. Write Operation Timing 1.9.2. Read Operation Timing
1.11. Pin Information x
1.11.1. Pin-Out Diagram for EPCQ16 and EPCQ32 Devices 1.11.2. Pin-Out Diagram for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices 1.11.3. EPCQ Device Pin Description
1.12. Device Package and Ordering Code x
1.12.1. Package 1.12.2. Ordering Code
1. Quad-Serial Configuration (EPCQ) Devices Datasheet

1.4.4. Address Range for EPCQ128

Table 11.  Address Range for Sectors 255..0 and Subsectors 4095..0 in EPCQ128 Devices
Sector Subsector Address Range (Byte Addresses in HEX)
Start End
255 4095 FFF000 FFFFFF
4094 FFE000 FFEFFF
. . .
4082 FF2000 FF2FFF
4081 FF1000 FF1FFF
4080 FF0000 FF0FFF
254 4079 FEF000 FEFFFF
4078 FEE000 FEEFFF
. . .
4066 FE2000 FE2FFF
4065 FE1000 FE1FFF
4064 FE0000 FE0FFF
129 2079 81F000 81FFFF
2078 81E000 81EFFF
. . .
2066 812000 812FFF
2065 811000 811FFF
2064 810000 810FFF
128 2063 80F000 80FFFF
2062 80E000 80EFFF
. . .
2050 802000 802FFF
2049 801000 801FFF
2048 800000 800FFF
127 2047 7FF000 7FFFFF
2046 7FE000 7FEFFF
. . .
2034 7F2000 7F2FFF
2033 7F1000 7F1FFF
2032 7F0000 7F0FFF
64 1039 40F000 40FFFF
1038 40E000 40EFFF
. . .
1026 402000 402FFF
1025 401000 401FFF
1024 400000 400FFF
63 1023 3FF000 3FFFFF
1022 3FE000 3FEFFF
. . .
1010 3F2000 3F2FFF
1009 3F1000 3F1FFF
1008 3F0000 3F0FFF
62 1007 3EF000 3EFFFF
1006 3EE000 3EEFFF
. . .
994 3E2000 3E2FFF
993 3E1000 3E1FFF
992 3E0000 3E0FFF
1 31 1F000 1FFFF
30 1E000 1EFFF
. . .
18 12000 12FFF
17 11000 11FFF
16 10000 10FFF
0 15 F000 FFFF
14 E000 EFFF
. . .
2 2000 2FFF
1 1000 1FFF
0 H'0000000 H'0000FFF
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