AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV Example of .jam File to Inject Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV

If you want to inject a single-bit error into the 7th bit of the 5th byte in the first data frame, you must shift in the data that contains the information of the injected error into the fault injection register.

The following figure shows the binary bit sequence 0 1000 0000 0100 0100 0000 is shifted into the fault injection register. Because bit 19 and bit 20 of the fault injection register is 01, a single-bit error is injected. The byte location of the injected error is defined as 000 0000 0100, thus the single-bit error is injected into the 5th byte of the data frame. The error byte location value is 0100 0000, which indicates the 7th bit of the 5th byte data is the specific location in which the single-bit error is injected.

Figure 11. Injecting a Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV DevicesFigure shows the error injection mechanism.

The following example shows the .jam file that you must execute in the EDERROR_INJECT JTAG instruction to inject the single-bit error into the first data frame for Arria® II, Stratix® III, and Stratix® IV devices.

Example of .jam File to Inject Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV Devices 

ACTION ERROR_INJECT = EXECUTE;

DATA DEVICE_DATA;

BOOLEAN out[21];

BOOLEAN in[21] = $080440;

ENDDATA;

PROCEDURE EXECUTE USES DEVICE_DATA;

BOOLEAN X = 0;

DRSTOP IDLE;

IRSTOP IDLE;

STATE IDLE;

IRSCAN 10, $015;

WAIT IDLE, 10 CYCLES, 1 USEC, IDLE;

DRSCAN 21, in[20..0], CAPTURE out[20..0];      ‘shift out the previous content from fault injection register

WAIT IDLE, 10 CYCLES, 1 USEC, IDLE;

DRSCAN 21, in[20..0], CAPTURE out[20..0];	‘shift out current content from fault injection register

WAIT IDLE, 10 CYCLES, 25 USEC, IDLE;

PRINT " ";

PRINT "Data read out from the FIR Register: ", out[20], out[19], " " ,out[18], out[17], out[16], out[15], out[14], out[13], out[12], out[11], out[10], out[9], out[8], " " , out[7], out[6], out[5], out[4], out[3], out[2], " ", out[1], out[0];

PRINT " ";

PRINT "Error Type:", out[20], out[19];

PRINT " ";

PRINT "Byte Location:", out[18], out[17], out[16], out[15], out[14], out[13], out[12], out[11], out[10], out[9], out[8];

PRINT " ";

PRINT "Error Byte Value:", out[7], out[6], out[5], out[4], out[3], out[2], out[1], out[0];

STATE IDLE;

EXIT 0;

ENDPROC;
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