AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.1. Functional Description

You can use the error detection CRC feature to detect errors in the FPGA configuration bits during configuration and user modes.

The width of the CRC field is 16 bits in Arria® II, Stratix® III, and Stratix® IV devices; 32 bits in Arria® V, Cyclone® V, and Stratix® V devices.

Figure 1. Error Detection Block DiagramFigure shows the error detection circuitry, syndrome registers, and error injection block.
  1. Applicable to the Arria® II, Stratix® III, and Stratix® IV devices only.
  2. Applicable to the Arria® V, Cyclone® V, and Stratix® V devices only.
Register Description
Syndrome Register This register contains the CRC signature of the current frame through the error detection verification cycle. The CRC_ERROR signal is derived from the contents in this register.
Error Message Register (EMR) This register contains information about the error type, the location of the error, and the actual syndrome. The types of errors and location reported are single- and double-adjacent bit errors. For Arria® V, Cyclone® V, and Stratix® V devices, the types of errors and location reported are single-, double-, triple-, and quadruple-adjacent bit errors. The location bits for other types of errors are not identified by the EMR. You can shift the contents of this register through the SHIFT_EDERROR_REG JTAG instruction or to the core through the core interface. See related information for more information about error message register.
JTAG Update Register This register is automatically updated with the contents of the EMR one cycle after the EMR register content is validated. The JTAG update register includes a clock enable that must be asserted before being sampled into the JTAG shift register. This requirement ensures that the JTAG update register is not being written by the contents of the EMR at exactly the same time as the JTAG shift register is reading its contents.
User Update Register This register is automatically updated with the contents of the EMR one cycle after the EMR register content is validated. The user update register includes a clock enable that must be asserted before being sampled into the user shift register. This requirement ensures that the user update register is not being written by the contents of the EMR at exactly the same time as the user shift register is reading its contents.
JTAG Shift Register This register is accessible by the JTAG interface and allows the contents of the JTAG update register to be sampled and read out by the SHIFT_EDERROR_REG JTAG instruction.
User Shift Register This register is accessible by the core logic and allows the contents of the user update register to be sampled and read by user logic.
JTAG Fault Injection Register This register is fully controlled by the EDERROR_INJECT JTAG instruction. This register holds the information of the error injection that you want in the bitstream.
Fault Injection Register The contents of the JTAG fault injection register is loaded into this fault injection register when the JTAG fault injection register is being updated.

Section Content
Configuration Error Detection
User Mode Error Detection
Error Detection Pin
Error Message Register
Error Detection Timing

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