1. Test Methodology of Error Detection and Recovery using CRC in...

AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075

Date 8/09/2019

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Document Table of Contents

Document Table of Contents x

1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x

1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.1. Functional Description x

1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing

1.1.4. Error Message Register x

1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices

1.3. Using the Error Detection CRC Feature x

1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host

1.3.1. Error Detection using User Logic x

1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals

1.3.2. Error Detection using an External Host x

1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host

1.4. Error Injection x

1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register

1.4.1. Fault Injection Register x

1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices

1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x

1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices

1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.1. Functional Description

1.1.1. Configuration Error Detection

1.1.2. User Mode Error Detection

1.1.3. Error Detection Pin

1.1.4. Error Message Register

1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices

1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices

1.1.5. Error Detection Timing

1.2. Error Correction

1.3. Using the Error Detection CRC Feature

1.3.1. Error Detection using User Logic

1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal

1.3.1.2. Unloading the EMR through User Logic

1.3.1.3. Accessing the Error Detection Block through User Logic

1.3.1.4. User Logic Control Block

1.3.1.5. User Logic Control Block Signals

1.3.2. Error Detection using an External Host

1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal

1.3.2.2. Unloading the EMR using an External Host

1.4. Error Injection

1.4.1. Fault Injection Register

1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices

1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices

1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction

1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV

1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices

1.4.3. Clearing Fault Injection Register

1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain

1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools

1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

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1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

This application note describes how to use the enhanced error detection cyclic redundancy check (CRC) feature in the Arria® II, Stratix® III, Stratix® IV, Arria® V, Cyclone® V, and Stratix® V devices. It also describes the test methodology you can use when testing the capability of this feature in the supported devices. Arria® V, Cyclone® V, and Stratix® V devices also support error correction feature.

During FPGA configuration, the error detection CRC feature detects configuration bitstream corruption when the bitstream is transferred from an external device into the FPGA. In user mode, the error detection CRC feature detects a single event upset (SEU) and determines the error type and location. In addition, Arria® V, Cyclone® V, and Stratix® V devices support internal scrubbing, an ability to correct errors detected in user mode.