F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 10/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Control and Status Registers 8. Designing with F-Tile Serial Lite IV Intel® FPGA IP 9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation 4.6. 32-bit Soft CWBIN Counters 4.7. i_stats_snapshot Port 4.8. Deterministic Latency
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Control and Status Registers x
7.1. F-Tile Serial Lite IV Intel® FPGA IP Soft CSR
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
8.1. Reset Guidelines 8.2. Error Handling Guidelines 8.3. Analog Parameter Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Control and Status Registers
8. Designing with F-Tile Serial Lite IV Intel® FPGA IP
9. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

6.3. MAC Signals

Table 24.  TX MAC Signals In this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description
tx_avs_ready 1 Output tx_core_clkout

Avalon® streaming signal.

When asserted, indicates that the TX MAC is ready to accept data.

tx_avs_data

  • 64*N (1 Gb to <29 Gb)
  • (64*N)*2 (29 Gb to <58 Gb)
  • (64*N)*4 (≥59 Gb)
Input tx_core_clkout

Avalon® streaming signal.

TX data.
tx_avs_channel 8 Input tx_core_clkout

Avalon® streaming signal.

The channel number for data being transferred on the current cycle.

This signal is not available in Basic mode.

tx_avs_valid 1 Input tx_core_clkout

Avalon® streaming signal.

When asserted, indicates the TX data signal is valid.

tx_avs_startofpacket 1 Input tx_core_clkout

Avalon® streaming signal.

When asserted, indicates the start of a TX data packet.

Assert for only a single clock cycle for each packet.

This signal is not available in Basic mode.

tx_avs_endofpacket 1 Input tx_core_clkout

Avalon® streaming signal.

When asserted, indicates the end of a TX data packet.

Assert for only a single clock cycle for each packet.

This signal is not available in Basic mode.

tx_avs_empty 5 Input tx_core_clkout

Avalon® streaming signal.

Indicates the number of non-valid words in the final burst of the TX data.

This signal is not available in Basic mode.

tx_num_valid_bytes_eob 4 Input tx_core_clkout

Indicates the number of valid bytes in the last word of the final burst.

This signal is not available in Basic mode.

tx_is_usr_cmd 1 Input tx_core_clkout

When asserted, this signal initiate a user-defined information cycle.

Assert this signal at the same clock cycle as tx_startofpacket assertion.

This signal is not available in Basic mode.

tx_link_up 1 Output tx_core_clkout

When asserted, indicates the TX data link is ready for data transmission.

tx_link_reinit 1 Output tx_core_clkout

When asserted, this signal initiates lanes re-alignment.

Assert this signal for one clock cycle to trigger the MAC to send ALIGN CW.

crc_error_inject N Input tx_core_clkout When asserted, the MAC injects a CRC32 error to selected lanes.
tx_error 5 Output tx_core_clkout Not used.

The following timing diagram shows an example of TX data transmissions of 10 words from user logic across 10 TX serial lanes.

Figure 27. TX Data Transmission Timing Diagram
Table 25.  RX MAC SignalsIn this table, N represents the number of lanes set in the IP parameter editor.
Name Width Direction Clock Domain Description
rx_avs_ready 1 Input rx_core_clkout

Avalon® streaming signal.

When asserted, indicates that the user logic is ready to accept data.

rx_avs_data

  • 64*N (1 Gb to <29 Gb)
  • (64*N)*2 (29 Gb to <58 Gb)
  • (64*N)*4 (≥59 Gb)
Output rx_core_clkout

Avalon® streaming signal.

RX data.
rx_avs_channel 8 Output rx_core_clkout

Avalon® streaming signal.

The channel number for data being received on the current cycle.

This signal is not available in Basic mode.
rx_avs_valid 1 Output rx_core_clkout

Avalon® streaming signal.

When asserted, indicates the RX data signal is valid.

rx_avs_startofpacket 1 Output rx_core_clkout

Avalon® streaming signal.

When asserted, indicates the start of an RX data packet.

Assert for only a single clock cycle for each packet.

This signal is not available in Basic mode.
rx_avs_endofpacket 1 Output rx_core_clkout

Avalon® streaming signal.

When asserted, indicates the end of an RX data packet.

Assert for only a single clock cycle for each packet.

This signal is not available in Basic mode.
rx_avs_empty 5 Output rx_core_clkout

Avalon® streaming signal.

Indicates the number of non-valid words in the final burst of the RX data.

This signal is not available in Basic mode.
rx_num_valid_bytes_eob 4 Output rx_core_clkout

Indicates the number of valid bytes in the last word of the final burst.

This signal is not available in Basic mode.
rx_is_usr_cmd 1 Output rx_core_clkout

When asserted, this signal initiate a user-defined information cycle.

Assert this signal at the same clock cycle as tx_startofpacket assertion.

This signal is not available in Basic mode.
rx_link_up 1 Output rx_core_clkout

When asserted, indicates the RX data link is ready for data reception.
rx_link_reinit 1 Input rx_core_clkout

When asserted, this signal initiates lanes re-alignment.

If you disable Enable Auto Alignment, assert this signal for one clock cycle to trigger the MAC to re-align the lanes. If the Enable Auto Alignment is set, the MAC re-align the lanes automatically.

Do not assert this signal when Enable Auto Alignment is set.

rx_error
  • (N*2)+2 (1 Gb to <29 Gb)
  • (N*2*2)+2 (29 Gb to <58 Gb)
  • (N*2*4)+2 (≥58 Gb)
Output rx_core_clkout

When asserted, indicates error conditions occur in the RX datapath.

  • [(N*2+2):N+3] = Indicates PCS error for specific lane.
  • [N+2] = Indicates alignment error. Re-initialize lane alignment if this bit is asserted.
  • [N+1]= Indicates data is forwarded to the user logic when user logic is not ready.
  • [N] = Indicates loss of alignment.
  • [(N-1):0] = Indicates the data contains CRC error.
sysref 1 Input

tx_core_clk

tx_core_clkout

Periodic pulse signal from external SYSREF pulse generator module with the pulse period of at least 1024 tx_core_clk and clock domain= tx_core_clkout . The F-Tile Serial Lite IV Intel® FPGA IP alignment marker period will follow this input sysref pulse period to align the CW insertion at the sysref event, ensuring the deterministic latency operation across the link.

Only available for Deterministic Latency enabled.
Level Two Title