F-Tile Serial Lite IV Intel® FPGA IP User Guide

Download PDF
ID 683074
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP
8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

2.5. Resource Utilization and Latency

The resources and latency for the F-Tile Serial Lite IV Intel® FPGA IP were obtained from the Intel® Quartus® Prime Pro Edition software version 22.2.

Table 6.   Intel® Agilex™ F-Tile Serial Lite IV Intel® FPGA IP Resource UtilizationThe latency measurement is based on the round trip latency from the TX core input to the RX core output.
Transceiver Type Variant Number of Data Lanes Mode RS-FEC ALM Dedicated Logic Registers ALUTs Memory 20K Latency (TX core clock cycle)
FGT 28.05 Gbps NRZ 16 Basic Disabled 7,128 24,422 3,915 0 77
16 Full Disabled 7,554 24,829 4,055 0 77
16 Basic Enabled 7,282 24,797 4,033 0 202
16 Full Enabled 7,667 25,157 4,182 0 202
58 Gbps PAM4 12 Basic Enabled 12,846 40,671 6,696 0 161
12 Full Enabled 13,693 41,972 6,886 0 161
FHT 29 Gbps NRZ 4 Basic Disabled 1,817 6,331 1,140 0 80
4 Full Disabled 2,031 6,554 1,216 0 80
4 Basic Enabled 1,877 6,439 1,194 0 204
4 Full Enabled 2,080 6,704 1,278 0 204
58 Gbps NRZ 4 Basic Enabled 4,425 13,784 2,444 0 154
4 Full Enabled 4,712 14,323 2,539 0 154
58 Gbps PAM4 4 Basic Enabled 4,422 13,795 2,441 0 164
4 Full Enabled 4,725 14,307 2,537 0 164
116 Gbps PAM4 4 Basic Enabled 8,482 26,408 4,163 0 135
4 Full Enabled 8,854 27,318 4,288 0 135
Level Two Title