F-Tile Serial Lite IV Intel® FPGA IP User Guide

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ID 683074
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide 2. F-Tile Serial Lite IV Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Parameters 6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals 7. Designing with F-Tile Serial Lite IV Intel® FPGA IP 8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview x
2.1. Release Information 2.2. Supported Features 2.3. IP Version Support Level 2.4. Device Speed Grade Support 2.5. Resource Utilization and Latency 2.6. Bandwidth Efficiency
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Parameters and Options 3.3. Generated File Structure 3.4. Simulating Intel® FPGA IP Cores 3.5. Synthesizing IP Cores in Other EDA Tools 3.6. Compiling the Full Design
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.4. Simulating Intel® FPGA IP Cores x
3.4.1. Simulating and Verifying the Design
4. Functional Description x
4.1. TX Datapath 4.2. RX Datapath 4.3. F-Tile Serial Lite IV Intel® FPGA IP Clock Architecture 4.4. Reset and Link Initialization 4.5. Link Rate and Bandwidth Efficiency Calculation
4.1. TX Datapath x
4.1.1. TX MAC Adapter 4.1.2. Control Word (CW) Insertion 4.1.3. TX CRC 4.1.4. TX MII Encoder 4.1.5. TX PCS and PMA
4.1.2. Control Word (CW) Insertion x
4.1.2.1. Start-of-burst CW 4.1.2.2. End-of-burst CW 4.1.2.3. Alignment Paired CW 4.1.2.4. Empty-cycle CW 4.1.2.5. Idle CW 4.1.2.6. Data Word
4.2. RX Datapath x
4.2.1. RX PCS and PMA 4.2.2. RX MII Decoder 4.2.3. RX CRC 4.2.4. RX Deskew 4.2.5. RX CW Removal
4.4. Reset and Link Initialization x
4.4.1. TX Reset and Initialization Sequence 4.4.2. RX Reset and Initialization Sequence
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. MAC Signals 6.4. Transceiver Reconfiguration Signals 6.5. PMA Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP x
7.1. Reset Guidelines 7.2. Error Handling Guidelines
1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide
2. F-Tile Serial Lite IV Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Parameters
6. F-Tile Serial Lite IV Intel® FPGA IP Interface Signals
7. Designing with F-Tile Serial Lite IV Intel® FPGA IP
8. F-Tile Serial Lite IV Intel® FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP User Guide

1. About the F-Tile Serial Lite IV Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 22.2
IP Version 6.0.0

This document describes IP features, architecture description, steps to generate, and guidelines to design the F-Tile Serial Lite IV Intel® FPGA IP using the F-tile transceivers in Intel® Agilex™ devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during the system-level design planning phase
  • Hardware designers when integrating the IP into their system-level design
  • Validation engineers during the system-level simulation and hardware validation phases

Related Documents

The following table lists other reference documents that are related to the F-Tile Serial Lite IV Intel® FPGA IP.
Table 1.  Related Documents
Reference Description
F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide This document provides generation, usage guidelines, and functional description of the F-Tile Serial Lite IV Intel® FPGA IP design examples in Intel® Agilex™ devices.
Intel® Agilex™ Device Data Sheet

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface
Level Two Title