F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Interface Signals 2.3. Register Map 2.4. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1.1. Hardware and Software Requirements

To test the example design, use the following hardware and software:
  • Intel® Quartus® Prime Pro Edition software version 21.3
  • System Console
  • Supported Simulator:
    • Synopsys* VCS*
    • Synopsys* VCS* MX
    • Siemens* EDA ModelSim* SE or Questa*
Note: Hardware support for design example will be available in the Intel® Quartus® Prime Pro Edition software version 21.4.
Level Two Title