F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Interface Signals 2.3. Register Map 2.4. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.04 21.3 3.0.0
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the supported simulator list in section: Hardware and Software Requirements.
  • Added new reset registers in section: Register Map.
2021.06.21 21.2 2.0.0 Initial release.
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