F-Tile Interlaken Intel® FPGA IP Design Example User Guide

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ID 683069
Date 10/04/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Design Example
2. Design Example Description x
2.1. Design Example Components 2.2. Interface Signals 2.3. Register Map 2.4. Reset
1. Quick Start Guide
2. Design Example Description
3. F-Tile Interlaken Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile Interlaken Intel® FPGA IP Design Example User Guide

2.1. Design Example Components

The example design connects system and PLL reference clocks and required design components. The example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.

After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.

The F-Tile Interlaken Intel® IP design example includes the following components:
  1. F-Tile Interlaken Intel® FPGA IP core
  2. Packet Generator and Packet Checker
  3. F-Tile Reference and System PLL Clocks Intel® FPGA IP core
Level Two Title