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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.3.7.5. Multicycle Exception Examples
The examples in this section illustrate how the multicycle exceptions affect the default setup and hold analysis in the Timing Analyzer. The multicycle exceptions apply to a simple register-to-register circuit. Both the source and destination clocks are set to 10 ns.
Section Content
Default Multicycle Analysis
End Multicycle Setup = 2 and End Multicycle Hold = 0
End Multicycle Setup = 2 and End Multicycle Hold = 1
Same Frequency Clocks with Destination Clock Offset
Destination Clock Frequency is a Multiple of the Source Clock Frequency
Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
Source Clock Frequency is a Multiple of the Destination Clock Frequency
Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset