Visible to Intel only — GUID: mwh1410383828780
Ixiasoft
Visible to Intel only — GUID: mwh1410383828780
Ixiasoft
2.3.7.5.1. Default Multicycle Analysis
The source and the destination timing waveform for the source register and destination register, respectively where HC1 and HC2 are hold checks 1 and 2 and SC is the setup check.
The most restrictive setup relationship with the default single-cycle analysis, that is, a setup relationship with an end multicycle setup assignment of one, is 10 ns.
The setup report for the default setup in the Timing Analyzer with the launch and latch edges highlighted.
The most restrictive hold relationship with the default single-cycle analysis, that a hold relationship with an end multicycle hold assignment of zero, is 0 ns.
The hold report for the default setup in the Timing Analyzer with the launch and latch edges highlighted.