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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.3.4. Creating Clocks and Clock Constraints
You must define all clocks and any associated clock characteristics, such as uncertainty, latency or skew. The Timing Analyzer supports .sdc commands that accommodate various clocking schemes, such as:
- Base clocks
- Virtual clocks
- Multifrequency clocks
- Generated clocks