Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer

ID 683068
Date 2/21/2024
Public
Document Table of Contents

2.3.4.5. Creating Clock Groups (set_clock_groups)

The Set Clock Groups (set_clock_groups) constraint allows you specify which clocks in the design are unrelated. By default, the Timing Analyzer assumes that all clocks with a common base or parent clock are related, and that all transfers between those clock domains are valid for timing analysis. You can exclude transfers between specific clock domains from timing analysis by cutting clock groups.

The set_clock_groups command allows you to cut timing between unrelated clocks in different groups. The Timing Analyzer performs the same analysis regardless of whether you specify -exclusive or -asynchronous groups. You define a group with the -group option. The Timing Analyzer excludes the timing paths between clocks for each of the separate groups.

The following tables show the impact of set_clock_groups.

Table 7.  set_clock_groups -group A
Dest\Source A B C D
A Analyzed Cut Cut Cut
B Cut Analyzed Analyzed Analyzed
C Cut Analyzed Analyzed Analyzed
D Cut Analyzed Analyzed Analyzed
Table 8.  set_clock_groups -group {A B}
Dest\Source A B C D
A Analyzed Analyzed Cut Cut
B Analyzed Analyzed Cut Cut
C Cut Cut Analyzed Analyzed
D Cut Cut Analyzed Analyzed
Table 9.  set_clock_groups -group A -group B
Dest\Source A B C D
A Analyzed Cut Cut Cut
B Cut Analyzed Cut Cut
C Cut Cut Analyzed Analyzed
D Cut Cut Analyzed Analyzed
Table 10.  set_clock_groups -group {A C} -group {B D}
Dest\Source A B C D
A Analyzed Cut Analyzed Cut
B Cut Analyzed Cut Analyzed
C Analyzed Cut Analyzed Cut
D Cut Analyzed Cut Analyzed
Table 11.  set_clock_groups -group {A C D}
Dest\Source A B C D
A Analyzed Cut Analyzed Analyzed
B Cut Analyzed Cut Cut
C Analyzed Cut Analyzed Analyzed
D Analyzed Cut Analyzed Analyzed