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2.3.1. Recommended Initial SDC Constraints
2.3.2. SDC File Precedence
2.3.3. Iterative Constraint Modification
2.3.4. Creating Clocks and Clock Constraints
2.3.5. Creating I/O Constraints
2.3.6. Creating Delay and Skew Constraints
2.3.7. Creating Timing Exceptions
2.3.8. Example Circuit and SDC File
2.3.7.5.1. Default Multicycle Analysis
2.3.7.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.3.7.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.3.7.5.4. Same Frequency Clocks with Destination Clock Offset
2.3.7.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.3.7.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.3.7.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.3.7.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
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2.3.4.5. Creating Clock Groups (set_clock_groups)
The Set Clock Groups (set_clock_groups) constraint allows you specify which clocks in the design are unrelated. By default, the Timing Analyzer assumes that all clocks with a common base or parent clock are related, and that all transfers between those clock domains are valid for timing analysis. You can exclude transfers between specific clock domains from timing analysis by cutting clock groups.
The set_clock_groups command allows you to cut timing between unrelated clocks in different groups. The Timing Analyzer performs the same analysis regardless of whether you specify -exclusive or -asynchronous groups. You define a group with the -group option. The Timing Analyzer excludes the timing paths between clocks for each of the separate groups.
The following tables show the impact of set_clock_groups.
Dest\Source | A | B | C | D |
A | Analyzed | Cut | Cut | Cut |
B | Cut | Analyzed | Analyzed | Analyzed |
C | Cut | Analyzed | Analyzed | Analyzed |
D | Cut | Analyzed | Analyzed | Analyzed |
Dest\Source | A | B | C | D |
A | Analyzed | Analyzed | Cut | Cut |
B | Analyzed | Analyzed | Cut | Cut |
C | Cut | Cut | Analyzed | Analyzed |
D | Cut | Cut | Analyzed | Analyzed |
Dest\Source | A | B | C | D |
A | Analyzed | Cut | Cut | Cut |
B | Cut | Analyzed | Cut | Cut |
C | Cut | Cut | Analyzed | Analyzed |
D | Cut | Cut | Analyzed | Analyzed |
Dest\Source | A | B | C | D |
A | Analyzed | Cut | Analyzed | Cut |
B | Cut | Analyzed | Cut | Analyzed |
C | Analyzed | Cut | Analyzed | Cut |
D | Cut | Analyzed | Cut | Analyzed |
Dest\Source | A | B | C | D |
A | Analyzed | Cut | Analyzed | Analyzed |
B | Cut | Analyzed | Cut | Cut |
C | Analyzed | Cut | Analyzed | Analyzed |
D | Analyzed | Cut | Analyzed | Analyzed |