Intel® MAX® 10 Clocking and PLL User Guide

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ID 683047
Date 12/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Clocking and PLL Overview 2. Intel® MAX® 10 Clocking and PLL Architecture and Features 3. Intel® MAX® 10 Clocking and PLL Design Considerations 4. Intel® MAX® 10 Clocking and PLL Implementation Guides 5. ALTCLKCTRL Intel® FPGA IP References 6. Avalon ALTPLL Intel® FPGA IP References 7. Avalon ALTPLL RECONFIG Intel® FPGA IP References 8. Internal Oscillator Intel® FPGA IP References 9. Intel® MAX® 10 Clocking and PLL User Guide Archives 10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide
1. Intel® MAX® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. Internal Oscillator Overview 1.3. PLLs Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. Internal Oscillator Architecture and Features 2.3. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Global Clock Networks 2.1.2. Clock Pins Introduction 2.1.3. Clock Resources 2.1.4. Global Clock Network Sources 2.1.5. Global Clock Control Block 2.1.6. Global Clock Network Power Down 2.1.7. Clock Enable Signals
2.3. PLLs Architecture and Features x
2.3.1. PLL Architecture 2.3.2. PLL Features 2.3.3. PLL Locations 2.3.4. Clock Pin to PLL Connections 2.3.5. PLL Counter to GCLK Connections 2.3.6. PLL Control Signals 2.3.7. Clock Feedback Modes 2.3.8. PLL External Clock Output 2.3.9. ADC Clock Input from PLL 2.3.10. Spread-Spectrum Clocking 2.3.11. PLL Programmable Parameters 2.3.12. Clock Switchover 2.3.13. PLL Cascading 2.3.14. PLL Reconfiguration
2.3.7. Clock Feedback Modes x
2.3.7.1. Source Synchronous Mode 2.3.7.2. No Compensation Mode 2.3.7.3. Normal Mode 2.3.7.4. Zero-Delay Buffer Mode
2.3.11. PLL Programmable Parameters x
2.3.11.1. Programmable Duty Cycle 2.3.11.2. Programmable Bandwidth 2.3.11.3. Programmable Phase Shift
2.3.12. Clock Switchover x
2.3.12.1. Automatic Clock Switchover 2.3.12.2. Automatic Switchover with Manual Override 2.3.12.3. Manual Clock Switchover
2.3.13. PLL Cascading x
2.3.13.1. PLL-to-PLL Cascading 2.3.13.2. Counter-to-Counter Cascading
3. Intel® MAX® 10 Clocking and PLL Design Considerations x
3.1. Clock Networks Design Considerations 3.2. Internal Oscillator Design Considerations 3.3. PLLs Design Considerations
3.1. Clock Networks Design Considerations x
3.1.1. Guideline: Clock Enable Signals 3.1.2. Guideline: Connectivity Restrictions
3.2. Internal Oscillator Design Considerations x
3.2.1. Guideline: Connectivity Restrictions
3.3. PLLs Design Considerations x
3.3.1. Guideline: PLL Control Signals 3.3.2. Guideline: Connectivity Restrictions 3.3.3. Guideline: Self-Reset 3.3.4. Guideline: Output Clocks 3.3.5. Guideline: PLL Cascading 3.3.6. Guideline: Clock Switchover 3.3.7. Guideline: .mif Streaming in PLL Reconfiguration 3.3.8. Guideline: scandone Signal for PLL Reconfiguration
4. Intel® MAX® 10 Clocking and PLL Implementation Guides x
4.1. ALTCLKCTRL Intel® FPGA IP 4.2. Avalon ALTPLL Intel® FPGA IP 4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP 4.4. Internal Oscillator Intel® FPGA IP
4.2. Avalon ALTPLL Intel® FPGA IP x
4.2.1. Expanding the PLL Lock Range 4.2.2. Programmable Bandwidth with Advanced Parameters 4.2.3. PLL Dynamic Reconfiguration Implementation 4.2.4. Dynamic Phase Configuration Implementation
4.2.3. PLL Dynamic Reconfiguration Implementation x
4.2.3.1. Post-Scale Counters (C0 to C4) 4.2.3.2. Scan Chain 4.2.3.3. Charge Pump and Loop Filter 4.2.3.4. Bypassing PLL Counter
4.2.4. Dynamic Phase Configuration Implementation x
4.2.4.1. Dynamic Phase Configuration Counter Selection 4.2.4.2. Dynamic Phase Configuration with Advanced Parameters
4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP x
4.3.1. Obtaining the Resource Utilization Report
5. ALTCLKCTRL Intel® FPGA IP References x
5.1. ALTCLKCTRL Intel® FPGA IP Parameters 5.2. ALTCLKCTRL Intel® FPGA IP Ports and Signals
6. Avalon ALTPLL Intel® FPGA IP References x
6.1. Avalon ALTPLL Intel® FPGA IP Parameters 6.2. Avalon ALTPLL Intel® FPGA IP Ports and Signals
6.1. Avalon ALTPLL Intel® FPGA IP Parameters x
6.1.1. Operation Modes Parameter Settings 6.1.2. PLL Control Signals Parameter Settings 6.1.3. Programmable Bandwidth Parameter Settings 6.1.4. Clock Switchover Parameter Settings 6.1.5. PLL Dynamic Reconfiguration Parameter Settings 6.1.6. Dynamic Phase Configuration Parameter Settings 6.1.7. Output Clocks Parameter Settings
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References x
7.1. Avalon ALTPLL RECONFIG Intel® FPGA IP Parameters 7.2. Avalon ALTPLL RECONFIG Intel® FPGA IP Ports and Signals 7.3. Avalon ALTPLL RECONFIG Intel® FPGA IP Counter Settings
8. Internal Oscillator Intel® FPGA IP References x
8.1. Internal Oscillator Intel® FPGA IP Parameters 8.2. Internal Oscillator Intel® FPGA IP Ports and Signals
1. Intel® MAX® 10 Clocking and PLL Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features
3. Intel® MAX® 10 Clocking and PLL Design Considerations
4. Intel® MAX® 10 Clocking and PLL Implementation Guides
5. ALTCLKCTRL Intel® FPGA IP References
6. Avalon ALTPLL Intel® FPGA IP References
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References
8. Internal Oscillator Intel® FPGA IP References
9. Intel® MAX® 10 Clocking and PLL User Guide Archives
10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide

4.2.3. PLL Dynamic Reconfiguration Implementation

To reconfigure the PLL counters, perform the following steps:

  1. Assert the scanclkena signal at least one scanclk cycle prior to shifting in the first bit of scandata (Dn).
  2. Shift the serial data (scandata) into the scan chain on the second rising edge of scanclk.
  3. After all 144 bits have been scanned into the scan chain, deassert the scanclkena signal to prevent inadvertent shifting of bits in the scan chain.
  4. Assert the configupdate signal for one scanclk cycle to update the PLL counters with the contents of the scan chain.
    The scandone signal goes high indicating that the PLL is being reconfigured. A falling edge indicates that the PLL counters have been updated with new settings.
  5. Reset the PLL using the areset signal if you make any changes to the M, N, post-scale output C counters, or the ICP , R, and C settings.
  6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
Figure 26. PLL Reconfiguration Scan Chain Functional Simulation

When reconfiguring the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface. You can reconfigure phase shifts in real time using the dynamic phase shift reconfiguration interface. If you want to keep the same nonzero phase shift setting (for example, 90°) on the clock output, you must reconfigure the phase shift after reconfiguring the counter clock frequency.


Section Content
Post-Scale Counters (C0 to C4)
Scan Chain
Charge Pump and Loop Filter
Bypassing PLL Counter

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