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1. Intel® MAX® 10 Clocking and PLL Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features
3. Intel® MAX® 10 Clocking and PLL Design Considerations
4. Intel® MAX® 10 Clocking and PLL Implementation Guides
5. ALTCLKCTRL Intel® FPGA IP References
6. Avalon ALTPLL Intel® FPGA IP References
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References
8. Internal Oscillator Intel® FPGA IP References
9. Intel® MAX® 10 Clocking and PLL User Guide Archives
10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide
2.3.1. PLL Architecture
2.3.2. PLL Features
2.3.3. PLL Locations
2.3.4. Clock Pin to PLL Connections
2.3.5. PLL Counter to GCLK Connections
2.3.6. PLL Control Signals
2.3.7. Clock Feedback Modes
2.3.8. PLL External Clock Output
2.3.9. ADC Clock Input from PLL
2.3.10. Spread-Spectrum Clocking
2.3.11. PLL Programmable Parameters
2.3.12. Clock Switchover
2.3.13. PLL Cascading
2.3.14. PLL Reconfiguration
3.3.1. Guideline: PLL Control Signals
3.3.2. Guideline: Connectivity Restrictions
3.3.3. Guideline: Self-Reset
3.3.4. Guideline: Output Clocks
3.3.5. Guideline: PLL Cascading
3.3.6. Guideline: Clock Switchover
3.3.7. Guideline: .mif Streaming in PLL Reconfiguration
3.3.8. Guideline: scandone Signal for PLL Reconfiguration
6.1.1. Operation Modes Parameter Settings
6.1.2. PLL Control Signals Parameter Settings
6.1.3. Programmable Bandwidth Parameter Settings
6.1.4. Clock Switchover Parameter Settings
6.1.5. PLL Dynamic Reconfiguration Parameter Settings
6.1.6. Dynamic Phase Configuration Parameter Settings
6.1.7. Output Clocks Parameter Settings
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4.2.3.2. Scan Chain
The Intel® MAX® 10 PLLs have a 144-bit scan chain.
Block Name | Number of Bits | ||
---|---|---|---|
Counter | Control Bit | Total | |
C4 6 | 16 | 2 7 | 18 |
C3 | 16 | 27 | 18 |
C2 | 16 | 27 | 18 |
C1 | 16 | 27 | 18 |
C0 | 16 | 27 | 18 |
M | 16 | 27 | 18 |
N | 16 | 27 | 18 |
Charge Pump | 9 | 0 | 9 |
Loop Filter8 | 9 | 0 | 9 |
Total number of bits | 144 |
Figure 27. PLL Component Scan Chain Order
Figure 28. PLL Post-Scale Counter Scan Chain Bit Order
6 LSB bit for C4 low-count value is the first bit shifted into the scan chain.
7 These two control bits include rbypass, for bypassing the counter, and rselodd, for selecting the output clock duty cycle.
8 MSB bit for loop filter is the last bit shifted into the scan chain.