Intel® MAX® 10 Clocking and PLL User Guide

ID 683047
Date 12/26/2023
Public
Document Table of Contents

4.2.3.2. Scan Chain

The Intel® MAX® 10 PLLs have a 144-bit scan chain.

Table 7.  PLL Component Reprogramming Bits
Block Name Number of Bits
Counter Control Bit Total
C4 6 16 2 7 18
C3 16 27 18
C2 16 27 18
C1 16 27 18
C0 16 27 18
M 16 27 18
N 16 27 18
Charge Pump 9 0 9
Loop Filter8 9 0 9
Total number of bits 144
Figure 27. PLL Component Scan Chain Order
Figure 28. PLL Post-Scale Counter Scan Chain Bit Order
6 LSB bit for C4 low-count value is the first bit shifted into the scan chain.
7 These two control bits include rbypass, for bypassing the counter, and rselodd, for selecting the output clock duty cycle.
8 MSB bit for loop filter is the last bit shifted into the scan chain.