Intel® MAX® 10 Clocking and PLL User Guide

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ID 683047
Date 12/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Clocking and PLL Overview 2. Intel® MAX® 10 Clocking and PLL Architecture and Features 3. Intel® MAX® 10 Clocking and PLL Design Considerations 4. Intel® MAX® 10 Clocking and PLL Implementation Guides 5. ALTCLKCTRL Intel® FPGA IP References 6. Avalon ALTPLL Intel® FPGA IP References 7. Avalon ALTPLL RECONFIG Intel® FPGA IP References 8. Internal Oscillator Intel® FPGA IP References 9. Intel® MAX® 10 Clocking and PLL User Guide Archives 10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide
1. Intel® MAX® 10 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. Internal Oscillator Overview 1.3. PLLs Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. Internal Oscillator Architecture and Features 2.3. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Global Clock Networks 2.1.2. Clock Pins Introduction 2.1.3. Clock Resources 2.1.4. Global Clock Network Sources 2.1.5. Global Clock Control Block 2.1.6. Global Clock Network Power Down 2.1.7. Clock Enable Signals
2.3. PLLs Architecture and Features x
2.3.1. PLL Architecture 2.3.2. PLL Features 2.3.3. PLL Locations 2.3.4. Clock Pin to PLL Connections 2.3.5. PLL Counter to GCLK Connections 2.3.6. PLL Control Signals 2.3.7. Clock Feedback Modes 2.3.8. PLL External Clock Output 2.3.9. ADC Clock Input from PLL 2.3.10. Spread-Spectrum Clocking 2.3.11. PLL Programmable Parameters 2.3.12. Clock Switchover 2.3.13. PLL Cascading 2.3.14. PLL Reconfiguration
2.3.7. Clock Feedback Modes x
2.3.7.1. Source Synchronous Mode 2.3.7.2. No Compensation Mode 2.3.7.3. Normal Mode 2.3.7.4. Zero-Delay Buffer Mode
2.3.11. PLL Programmable Parameters x
2.3.11.1. Programmable Duty Cycle 2.3.11.2. Programmable Bandwidth 2.3.11.3. Programmable Phase Shift
2.3.12. Clock Switchover x
2.3.12.1. Automatic Clock Switchover 2.3.12.2. Automatic Switchover with Manual Override 2.3.12.3. Manual Clock Switchover
2.3.13. PLL Cascading x
2.3.13.1. PLL-to-PLL Cascading 2.3.13.2. Counter-to-Counter Cascading
3. Intel® MAX® 10 Clocking and PLL Design Considerations x
3.1. Clock Networks Design Considerations 3.2. Internal Oscillator Design Considerations 3.3. PLLs Design Considerations
3.1. Clock Networks Design Considerations x
3.1.1. Guideline: Clock Enable Signals 3.1.2. Guideline: Connectivity Restrictions
3.2. Internal Oscillator Design Considerations x
3.2.1. Guideline: Connectivity Restrictions
3.3. PLLs Design Considerations x
3.3.1. Guideline: PLL Control Signals 3.3.2. Guideline: Connectivity Restrictions 3.3.3. Guideline: Self-Reset 3.3.4. Guideline: Output Clocks 3.3.5. Guideline: PLL Cascading 3.3.6. Guideline: Clock Switchover 3.3.7. Guideline: .mif Streaming in PLL Reconfiguration 3.3.8. Guideline: scandone Signal for PLL Reconfiguration
4. Intel® MAX® 10 Clocking and PLL Implementation Guides x
4.1. ALTCLKCTRL Intel® FPGA IP 4.2. Avalon ALTPLL Intel® FPGA IP 4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP 4.4. Internal Oscillator Intel® FPGA IP
4.2. Avalon ALTPLL Intel® FPGA IP x
4.2.1. Expanding the PLL Lock Range 4.2.2. Programmable Bandwidth with Advanced Parameters 4.2.3. PLL Dynamic Reconfiguration Implementation 4.2.4. Dynamic Phase Configuration Implementation
4.2.3. PLL Dynamic Reconfiguration Implementation x
4.2.3.1. Post-Scale Counters (C0 to C4) 4.2.3.2. Scan Chain 4.2.3.3. Charge Pump and Loop Filter 4.2.3.4. Bypassing PLL Counter
4.2.4. Dynamic Phase Configuration Implementation x
4.2.4.1. Dynamic Phase Configuration Counter Selection 4.2.4.2. Dynamic Phase Configuration with Advanced Parameters
4.3. Avalon ALTPLL RECONFIG Intel® FPGA IP x
4.3.1. Obtaining the Resource Utilization Report
5. ALTCLKCTRL Intel® FPGA IP References x
5.1. ALTCLKCTRL Intel® FPGA IP Parameters 5.2. ALTCLKCTRL Intel® FPGA IP Ports and Signals
6. Avalon ALTPLL Intel® FPGA IP References x
6.1. Avalon ALTPLL Intel® FPGA IP Parameters 6.2. Avalon ALTPLL Intel® FPGA IP Ports and Signals
6.1. Avalon ALTPLL Intel® FPGA IP Parameters x
6.1.1. Operation Modes Parameter Settings 6.1.2. PLL Control Signals Parameter Settings 6.1.3. Programmable Bandwidth Parameter Settings 6.1.4. Clock Switchover Parameter Settings 6.1.5. PLL Dynamic Reconfiguration Parameter Settings 6.1.6. Dynamic Phase Configuration Parameter Settings 6.1.7. Output Clocks Parameter Settings
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References x
7.1. Avalon ALTPLL RECONFIG Intel® FPGA IP Parameters 7.2. Avalon ALTPLL RECONFIG Intel® FPGA IP Ports and Signals 7.3. Avalon ALTPLL RECONFIG Intel® FPGA IP Counter Settings
8. Internal Oscillator Intel® FPGA IP References x
8.1. Internal Oscillator Intel® FPGA IP Parameters 8.2. Internal Oscillator Intel® FPGA IP Ports and Signals
1. Intel® MAX® 10 Clocking and PLL Overview
2. Intel® MAX® 10 Clocking and PLL Architecture and Features
3. Intel® MAX® 10 Clocking and PLL Design Considerations
4. Intel® MAX® 10 Clocking and PLL Implementation Guides
5. ALTCLKCTRL Intel® FPGA IP References
6. Avalon ALTPLL Intel® FPGA IP References
7. Avalon ALTPLL RECONFIG Intel® FPGA IP References
8. Internal Oscillator Intel® FPGA IP References
9. Intel® MAX® 10 Clocking and PLL User Guide Archives
10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide

10. Document Revision History for the Intel® MAX® 10 Clocking and PLL User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.12.26 21.1
  • Text edits only; no new technical information.
  • Updated for latest branding standards.
2021.11.01 21.1
  • Added Y180 package information in the PLL Locations for 10M16, 10M25, 10M40, and 10M50 Devices diagram.
  • Added description about PLL_CLKOUTn pin support in the Zero-Delay Buffer Mode section.
2021.02.09 18.0
  • Updated the note in the PLL Locations for 10M02 (Single Power Supply U324 Package), 10M04, and 10M08 Devices diagram.
  • Updated the description for clkselect[] and inclk[] ports in the ALTCLKCTRL Input Ports for Intel® MAX® 10 Devices table.
2020.10.02 18.0 Updated the note to PLL 2, PLL 3, and PLL 4 in the PLL Locations for 10M16, 10M25, 10M40, and 10M50 Devices diagram.
2018.06.15 18.0
  • Added description in the Internal Oscillator Overview section.
  • Defined clkena signal in the Global Clock Network Power Down section.
  • Mentioned that the spread-spectrum signals must be generated externally in the Spread-Spectrum Clocking section.
  • Updated the Example of Automatic Switchover After Loss of Clock Detection diagram.
  • Corrected the parameter names in the Expanding the PLL Lock Range section.
  • Updated the description in the Bypassing PLL Counter section.
  • Defined tsu and th in the Dynamic Phase Configuration Implementation section.
  • Renamed the following IP cores as per Intel rebranding:
    • Renamed ALTCLKCTRL IP core to ALTCLKCTRL Intel FPGA IP core.
    • Renamed ALTPLL IP core to ALTPLL Intel FPGA IP core.
    • Renamed ALTPLL_RECONFIG IP core to ALTPLL_RECONFIG Intel FPGA IP core.
    • Renamed Internal Oscillator IP core to Internal Oscillator Intel FPGA IP core.
  • Updated SignalTap II to Signal Tap II.
Date Version Changes
December 2017 2017.12.29
  • Updated the title for the following PLL locations diagrams.
    • PLL Locations for 10M02 Device (Except Single Power Supply U324 Package)
    • PLL Locations for 10M02 (Single Power Supply U324 Package), 10M04, and 10M08 Devices
  • Updated dedicated clock input pins for PLL1 in the Clock Feedback Modes section.
  • Updated the description in the PLL External Clock Output section.
  • Updated the value and description for the Clock Frequency parameter in the Internal Oscillator IP Core Parameters for Intel® MAX® 10 Devices table.
  • Updated the following terms:
    • Changed Qsys to Platform Designer (Standard)
    • Changed TimeQuest Timing Analyzer to Timing Analyzer
February 2017 2017.02.21 Rebranded as Intel.
November 2015 2015.11.02
  • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to Introduction to Altera IP Cores.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12 Added connectivity restriction guideline to the PLL design considerations.
May 2015 2015.05.04 Rearranged the fine resolution phase shift equation.
December 2014 2014.12.15
  • Corrected the statement that if you do not use the dedicated clock input pins for clock input, you can also use them as general-purpose input or output pins.
  • Added description in Internal Oscillator Architecture and Features to state that the internal ring oscillator operates up to 232 MHz and this frequency is not accessible.
  • Added connectivity restrictions guideline for internal oscillator.
  • Added Internal Oscillator IP Core parameter: Clock Frequency.
  • Moved Internal Oscillator Frequencies table from Internal Oscillator Architecture and Features chapter to Intel® MAX® 10 FPGA Device Datasheet.
September 2014 2014.09.22 Initial release.
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