Ethernet Design Example Components User Guide

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ID 683044
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.6. Configuration Registers

Table 13.  Register Description
Word Offset Name Description Access HW Reset Value
0x00 SecondsH The upper 16-bit second field of the 96-bit TOD. The value occupies bits 0 to 15. Bits 16 to 31 are not used.

Read the TOD registers in this sequence: NanoSec, SecondsL, and SecondsH. 96-bit TOD is snapshot whenever the NanoSec register is read.

Write the TOD registers in this sequence: SecondsH, SecondsL, and NanoSec.

Reading the SecondsH, SecondsL, and NanoSec registers does not necessarily return the last values written to these registers.

RW 0x0
0x01 SecondsL The lower 32-bit second field of the 96-bit TOD.

To read from or write to the TOD registers, refer to the guidelines provided in the SecondsH register description.

RW 0x0
0x02 NanoSec The 32-bit nanosecond field of the 96-bit TOD. Loading this register with a value equal to or larger than a billion leads to an incorrect timestamp.

To read from or write to TOD registers, refer to the guidelines provided in the SecondsH register description.

RW 0x0
0x03 Reserved – – –
0x04 Period The period for the frequency adjustment.
  • Bits [24:16]: The nanosecond field if the PERIOD_CLOCK_FREQUENCY parameter is set to 0.
  • Bits [19:16]: The nanosecond field if the PERIOD_CLOCK_FREQUENCY parameter is set to 1.
  • Bits [15:0]: The fractional nanosecond field.
  • The remaining bits are not used.

The reset value of this register, n, is determined by the value of the DEFAULT_NSEC_PERIOD and DEFAULT_FNSEC_PERIOD parameters.

RW n
0x05 AdjustPeriod The period for the offset adjustment.
  • Bits [24:16]: The nanosecond field if the PERIOD_CLOCK_FREQUENCY parameter is set to 0.
  • Bits [19:16]: The nanosecond field if the PERIOD_CLOCK_FREQUENCY parameter is set to 1.
  • Bits [15:0]: The fractional nanosecond field.
  • The remaining bits are not used.

The reset value of this register, n, is determined by the value of the DEFAULT_NSEC_ADJPERIOD and DEFAULT_FNSEC_ADJPERIOD parameters.

For offset adjustment, write to AdjustPeriod register followed by AdjustCount register. The TOD offset adjustment starts after the AdjustCount register is written.

RW n
0x06 AdjustCount
  • Bits [31:20]: Not used.
  • Bits [19:0]: The number of clock cycles used during offset adjustment.

For offset adjustment, write to AdjustPeriod register followed by AdjustCount register. The TOD offset adjustment starts after the AdjustCount register is written.

RW 0x0
0x07 DriftAdjust The value that the TOD clock uses to periodically adjust the time of day.
  • Bits [31:20]: Not used.
  • Bits [19:16]: The nanosecond field.
  • Bits [15:0]: The fractional nanosecond field.
 RW 0x0
0x08 DriftAdjustRate
  • Bit 31: The drift direction: 0 for addition and 1 for subtraction.
  • Bits [30:16]: Not used.
  • Bits [15:0]: The interval between drift adjustments in number of clock cycles.

Writing a value other than 0 to this register triggers the drift adjustment.

 RW 0x0
0x09 OffsetNS
  • Bit 31: Not used.
  • Bit 30: The offset direction: 0 for addition and 1 for subtraction.
  • Bits [29:0]: The nanosecond field of the offset.

Writing a value other than 0 to this register triggers the offset in the time of day.

 RW 0x0
0x0A OffsetFNS
  • Bits [31:16]: Not used.
  • Bits [15:0]: The fractional nanosecond field of the offset.
 RW 0x0
0x0B routing_adj_val
  • Bits [31:20]: Unused
  • Bits [19:0]: routing_adj_val
  • This is a 20-bit register to adjust the routing delay of the pps (pulse per second) pulse. The routing adjustment register has two components, the nanosecond part, and the fractional part.
    • routing_adj_val[15:0]: fractional nanosecond part
    • routing_adj_val[19:16]: nanosecond part

      Example: if routing delay = 4.3 ns then,

      routing_adj_val[19:16] = 0x4

      routing_adj_val[15:0] = 0x4CCC (0.3 fns * 2^16 = 19660.8 in 16-bit decimal = 0x4CCC; ignore 0.8)

RW 0x0
0x0C JitterTimer
  • Bit 31: Unused
  • Bit 30: The direction of the jitter adjustment: 0 for addition and 1 for subtraction.
  • Bits [29:0]: The timer value in number of clock cycles.

Periodic jitter adjustment is disabled when this register is set to 0.

Writing a value other than 0 to this register enables period jitter adjustment. Hence, write to this register last.

 RW 0x0
0x0D JitterAdjust
  • Bits [31:16]: The nanosecond field of the jitter adjustment.
  • Bits [15:0]: The fractional nanosecond field of the jitter adjustment.
RW 0x0
0x10 WanderTimerLSB
  • Bit 31: Unused
  • Bit 30: The direction of the timer adjustment: 0 for addition and 1 for subtraction.
  • Bits [29:0]: The least significant byte of the timer in number of clock cycles.

Writing a value other than 0 to this register enables wander timer adjustment. Hence, write to the WanderTimerLSB and WanderTimerMSB registers last.

RW 0x0
0x11 WanderTimerMSB
  • Bits [31:16]: Unused.
  • Bits [15:0]: The most significant byte of the timer in number of clock cycles.
 RW 0x0
0x12 WanderAdjust
  • Bits [31:16]: The nanosecond field of the wander adjustment.
  • Bits [15:0]: The fractional nanosecond field of the wander adjustment.
 RW 0x0
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