P-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683038
Date 12/19/2022
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Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.6. Running the Design Example

Here are the test operations you can perform on the P-Tile Avalon® Streaming IP for PCIe design examples:
Table 3.  Test Operations Supported by the P-Tile Avalon® Streaming PCIe Design Examples
Operations Required BAR Supported by P-Tile Avalon® Streaming IP for PCIe Design Examples
PIO SR-IOV Performance
0: Link test - 100 writes and reads 0 Yes Yes No
1: Write memory space 0 Yes Yes No
2: Read memory space 0 Yes Yes No
3: Write configuration space N/A No No No
4: Read configuration space N/A No No No
5: Change BAR N/A Yes Yes No
6: Change device N/A Yes Yes No
7: Enable SR-IOV N/A No Yes No
8: Do a link test for every enabled virtual function belonging to the current device N/A No Yes No
9: Perform DMA for Throughput N/A No No Yes
For link stability when running the design examples on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ F-Series FPGA Development Kit, set the PCIe refclk switch to select the common refclk from the PCIe Edge Connector.
  • For the Intel® Stratix® 10 DX FPGA Development Kit, set SW14 to the OFF position to select the common refclk with the PCIe Host.
  • For the Intel® Agilex™ F-Series FPGA Development Kit, set SW7.1 to the OFF position to select the common refclk with the PCIe Host.

Section Content
Running the PIO Design Example
Running the SR-IOV Design Example
Running the Performance Design Example

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