P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 683038
Date 4/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples x
1.1. Overview 1.2. Functional Description for the Programmed Input/Output (PIO) Design Example 1.3. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.4. Functional Description for the Performance Design Example 1.5. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulations 2.3.2. Testbench
2.3.1. Steps to Run Simulations x
2.3.1.1. Running Simulations Using QuestaSim* 2.3.1.2. Running Simulations Using VCS* 2.3.1.3. Running Simulations Using Riviera*
2.3.2. Testbench x
2.3.2.1. Test Driver Module 2.3.2.2. PIO Design Example Testbench 2.3.2.3. SR-IOV Design Example Testbench 2.3.2.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example 2.6.3. Running the Performance Design Example
1. About the P-tile Avalon® Streaming Intel® FPGA IP for PCI Express Design Examples
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

2.6.2. Running the SR-IOV Design Example

Here are the steps to test the SR-IOV design example on hardware:
  1. Run the Intel FPGA IP PCIe link test by running the sudo ./intel_fpga_pcie_link_test command and then select the option 1: Manually select a device.
  2. Enter the BDF of the physical function for which the virtual functions are allocated.
  3. Enter BAR “0” to proceed to the test menu.
  4. Enter option 7 to enable SR-IOV for the current device.
  5. Enter the number of virtual functions to be enabled for the current device.
    Note: To disable Virtual Functions (VFs), choose option 7 (Enable SR-IOV) and enter the value 0 when prompted for the number of VFs to enable for the current device.
  6. In a new terminal, run the lspci –d 1172: | grep -c “Altera” command to verify the enumeration of PFs and VFs. The expected result is the sum of the number of physical functions and number of virtual functions.

    Below is an example of a design with two PFs and two VFs, where each PF has one VF assigned to it.

    If you run the command lspci -d 1172:, you see the following: 

    08:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev01)

    (this BDF is for PF0) 

    08:00.1 Unassigned class [ff00]: Altera Corporation Device 0000

    (this BDF is for PF1) 

    08:00.2 Unassigned class [ff00]: Altera Corporation Device 0000

    (this BDF is for the VF of PF0) 

    08:00.3 Unassigned class [ff00]: Altera Corporation Device 0000

    (this BDF is for the VF of PF1)

    When you disable the VF for PF0, lspci -d 1172: shows the following: 

    08:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev01)
08:00.1 Unassigned class [ff00]: Altera Corporation Device 0000
08:00.3 Unassigned class [ff00]: Altera Corporation Device 0000

    When you disable the VFs for both PF0 and PF1, lspci -d 1172: shows the following: 

    08:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev01)
08:00.1 Unassigned class [ff00]: Altera Corporation Device 0000
  7. Enter option 8 to perform a link test for every enabled virtual function allocated for the physical function. The link test application does 100 memory writes with a single dword of data each and then reads the data back for checking. The application then prints the number of virtual functions that failed the link test at the end of the testing.

Level Two Title