Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example User Guide

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ID 683038
Date 12/15/2021
Public

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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide
1. Design Example Description x
1.1. Functional Description for the Programmed Input/Output (PIO) Design Example 1.2. Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example 1.3. Functional Description for the Performance Design Example 1.4. Hardware and Software Requirements
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Compiling the Design Example 2.5. Installing the Linux Kernel Driver 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Test Driver Module 2.3.1.2. PIO Design Example Testbench 2.3.1.3. SR-IOV Design Example Testbench 2.3.1.4. Performance Design Example Testbench
2.6. Running the Design Example x
2.6.1. Running the PIO Design Example 2.6.2. Running the SR-IOV Design Example
1. Design Example Description
2. Quick Start Guide
3. P-tile Avalon® Streaming IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the Intel® P-Tile Avalon® Streaming Hard IP for PCIe* Design Example User Guide

1.4. Hardware and Software Requirements

  • Intel® Quartus® Prime Pro Edition Software version 21.4
  • OS: CentOS Linux 7.0
  • Kernel: 3.10.514
  • Intel® Stratix® 10 DX ES/Production or Intel® Agilex™ F-Series ES FPGA Development Kit supporting P-Tile PCIe Gen4 / Gen3

For details on the design example simulation steps and how to run Hardware tests, refer to Quick Start Guide.

For more information on development kits, refer to FPGA Development Kits on the Intel web site.

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