Visible to Intel only — GUID: fgl1549003683360
Ixiasoft
Visible to Intel only — GUID: fgl1549003683360
Ixiasoft
3.2.2.5. FP16 Vector One Mode
This mode performs a summation of two half-precision multiplications with the chainin input from the previous variable DSP Block. The output is a single-precision floating-point value which is fed into chainout.
Chainin Parameter | Vector One with Floating-point Addition | Vector One with Floating-point Subtraction |
---|---|---|
Disable | fp32_result = (fp16_mult_top_a * fp16_mult_top_b) + (fp16_mult_bot_a * fp16_mult_bot_b) fp32_chainout = fp32_adder_a |
fp32_result = (fp16_mult_top_a * fp16_mult_top_b) - (fp16_mult_bot_a * fp16_mult_bot_b) fp32_chainout = fp32_adder_a |
Enable | fp32_result = (fp16_mult_top_a * fp16_mult_top_b) + (fp16_mult_bot_a * fp16_mult_bot_b) + fp32_chainin fp32_chainout = fp32_adder_a |
fp32_result = (fp16_mult_top_a * fp16_mult_top_b) - (fp16_mult_bot_a * fp16_mult_bot_b) - fp32_chainin fp32_chainout = fp32_adder_a |
- fp16_mult_top_invalid
- fp16_mult_top_inexact
- fp16_mult_top_overflow
- fp16_mult_top_underflow
- fp16_mult_bot_invalid
- fp16_mult_bot_inexact
- fp16_mult_bot_overflow
- fp16_mult_bot_underflow
- fp16_adder_invalid
- fp16_adder_inexact
- fp16_adder_overflow
- fp16_adder_underflow
- fp32_adder_invalid
- fp32_adder_inexact
- fp32_adder_overflow
- fp32_adder_underflow
- fp16_mult_top_invalid
- fp16_mult_top_inexact
- fp16_mult_top_infinite
- fp16_mult_top_zero
- fp16_mult_bot_invalid
- fp16_mult_bot_inexact
- fp16_mult_bot_infinite
- fp16_mult_bot_zero
- fp16_adder_invalid
- fp16_adder_inexact
- fp16_adder_infinite
- fp16_adder_zero
- fp32_adder_invalid
- fp32_adder_inexact
- fp32_adder_overflow
- fp32_adder_underflow