Visible to Intel only — GUID: lcl1564732163580
Ixiasoft
Visible to Intel only — GUID: lcl1564732163580
Ixiasoft
5.6.3. 18 × 18 Sum of Two Mode Signals
Signal Name | Type | Width | Description |
---|---|---|---|
ax[17:0] | Input | 18 | Input data bus to top multiplier. This signal is not available when internal coefficient feature is enabled. |
ay[18:0] | Input | 19 | Input data bus to top multiplier. When pre-adder is enabled, these signals are served as input to the top pre-adder. |
az[17:0] | Input | 18 | These signal are input to the top pre-adder. These signals are only available when pre-adder is enabled. |
bx[17:0] | Input | 18 | Input data bus to bottom multiplier. |
by[18:0] | Input | 19 | Input data bus to bottom multiplier. When pre-adder is enabled, these signals serve as input signals to the bottom pre-adder. |
bz[17:0] | Input | 18 | These signals are input signals to the bottom pre-adder. These signals are only available when pre-adder is enabled. |
resulta[63:0] | Output | 37 | Output data bus from top multiplier. |
Signal Name | Type | Width | Description |
---|---|---|---|
clk[0] | Input | 1 | Input clock for all registers. |
ena[2:0] | Input | 3 | Clock enable signals for all registers. These signals are active-High. |
clr[1:0] | Input | 2 | These signals can be asynchronous or synchronous clear input signals for all registers. You may select the type of clear input signal using Type of clear signal parameter. These signals are active-High. By default, this signal is low. For more information about clock enable restrictions for input registers, refer to the related information. |
Signal Name | Type | Width | Description |
---|---|---|---|
disable_chainout | Input | 1 | Dynamic input signal to enable dynamic chainout feature. You can change the value of this signal during run-time. You must connect the chainout output bus to the next DSP block in order to use this signal.
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disable_scanin | Input | 1 | Dynamic input signal to enable dynamic scanin feature. You can change the value of this signal during run-time. This signal is available when you Set Enable 'disable scanin parameter to Yes. You must set Enable input cascade for 'ay' input parameter to Yes to use this signal.
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accumulate | Input | 1 | Input signal to enable or disable the accumulator feature. You can change the value of this signal during run-time.
|
loadconst | Input | 1 | Input signal to enable or disable the load constant feature. You can change the value of this signal during run-time.
|
sub | Input | 1 | Dynamic input signal to control the operation of the adder module. You can change the value of this signal during run-time.
|
negate | Input | 1 | Dynamic input signal to control the operation of the chainout adder module. You can change the value of this signal during run-time.
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Signal Name | Type | Width | Description |
---|---|---|---|
coefsela[2:0] | Input | 3 | Input selection signals for 8 coefficient values defined by user for the top multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_a_0 to coef_a_7.
These signals are only available when the internal coefficient feature is enabled. |
coefselb[2:0] | Input | 3 | Input selection signals for 8 coefficient values defined by user for the bottom multiplier. The coefficient values are stored in the internal memory and specified by parameters coef_b_0 to coef_b_7.
These signals are only available when the internal coefficient feature is enabled. |
Signal Name | Type | Width | Description |
---|---|---|---|
scanin[18:0] | Input | 19 | Input data bus for input cascade module. Connect these signals to the scanout signals from the preceding DSP core. |
scanout[18:0] | Output | 19 | Output data bus of the input cascade module. Connect these signals to the scanin signals of the next DSP core. |
Signal Name | Type | Width | Description |
---|---|---|---|
chainin[63:0] | Input | 64 | Input data bus for output cascade module. Connect these signals to the chainout signals from the preceding DSP core. |
chainout[63:0] | Output | 64 | Output data bus of the output cascade module. Connect these signals to the chainin signals of the next DSP core. |