Intel® FPGA SDK for OpenCL™ Standard Edition: Cyclone® V SoC Getting Started Guide

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ID 683030
Date 4/20/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Cyclone V SoC Getting Started Guide 2. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Windows 3. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Linux A. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Cyclone® V SoC Getting Started Guide
1. Intel® FPGA SDK for OpenCL™ Standard Edition Cyclone V SoC Getting Started Guide x
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition 1.2. Contents of the Intel® FPGA SDK for OpenCL™ Standard Edition 1.3. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition and Cyclone® V SoC Development Kit Setup Processes 1.4. Overview of the Intel® FPGA SDK for OpenCL™ Cyclone V SoC Programming Flow 1.5. Cyclone V SoC Development Kit Reference Platform Board Variants 1.6. Cyclone V SoC FPGA-Specific OpenCL Design Considerations
2. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Windows x
2.1. Upgrading to Current Version of Intel FPGA SDK for OpenCL for Cyclone® V SoC FPGA 2.2. Downloading the Intel® FPGA SDK for OpenCL™ Standard Edition 2.3. Downloading the Intel® SoC FPGA Embedded Development Suite 2.4. Installing the Intel® FPGA SDK for OpenCL™ 2.5. Setting the Intel® FPGA SDK for OpenCL™ User Environment Variables for SoC FPGA 2.6. Installing the Intel® SoC FPGA Embedded Development Suite Standard Edition 2.7. Installing the Cyclone V SoC Development Kit 2.8. Downloading an OpenCL Design Example 2.9. Creating the Hardware Configuration File of an OpenCL Kernel for SoC FPGA 2.10. Executing an OpenCL Kernel on an SoC FPGA 2.11. Uninstalling the Software
2.7. Installing the Cyclone V SoC Development Kit x
2.7.1. Writing an SD Card Image onto the Micro SD Flash Card 2.7.2. Configuring the SW3 Switches 2.7.3. Setting Up Terminal Connection 2.7.4. Setting Environment Variables and Loading OpenCL Linux Kernel Driver 2.7.5. Connecting the Board to Network via Ethernet
2.7.5. Connecting the Board to Network via Ethernet x
2.7.5.1. Ensuring IP Address Acquisition 2.7.5.2. Using SSH and SCP
2.10. Executing an OpenCL Kernel on an SoC FPGA x
2.10.1. Building the Host Application 2.10.2. Running the Host Application 2.10.3. Output from Successful Kernel Execution on the Cyclone V SoC Development Kit
3. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Linux x
3.1. Upgrading to Current Version of Intel FPGA SDK for OpenCL for Cyclone® V SoC FPGA 3.2. Downloading the Intel® FPGA SDK for OpenCL™ Standard Edition 3.3. Downloading the Intel® SoC FPGA Embedded Development Suite 3.4. Installing the Intel® FPGA SDK for OpenCL™ 3.5. Setting the Intel® FPGA SDK for OpenCL™ User Environment Variables for SoC FPGA 3.6. Installing the Intel® SoC FPGA Embedded Development Suite Pro Edition 3.7. Installing the Cyclone V SoC Development Kit 3.8. Verifying Host Runtime Functionality via Emulation 3.9. Creating the Hardware Configuration File of an OpenCL Kernel for SoC FPGA 3.10. Executing an OpenCL Kernel on an SoC FPGA 3.11. Uninstalling the Software
3.7. Installing the Cyclone V SoC Development Kit x
3.7.1. Writing an SD Card Image onto the Micro SD Flash Card 3.7.2. Configuring the SW3 Switches 3.7.3. Setting Up Terminal Connection 3.7.4. Setting Environment Variables and Loading OpenCL Linux Kernel Driver 3.7.5. Connecting the Board to Network via Ethernet
3.7.5. Connecting the Board to Network via Ethernet x
3.7.5.1. Ensuring IP Address Acquisition 3.7.5.2. Mounting a Shared Drive 3.7.5.3. Using SSH and SCP
3.8. Verifying Host Runtime Functionality via Emulation x
3.8.1. Downloading an OpenCL Design Example 3.8.2. Compiling a Kernel for Emulation (-march=emulator) 3.8.3. Building the Host Application 3.8.4. Emulating Your OpenCL Kernel
3.10. Executing an OpenCL Kernel on an SoC FPGA x
3.10.1. Running the Host Application 3.10.2. Output from Successful Kernel Execution on the Cyclone V SoC Development Kit
1. Intel® FPGA SDK for OpenCL™ Standard Edition Cyclone V SoC Getting Started Guide
2. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Windows
3. Setting Up the Intel® FPGA SDK for OpenCL™ , Intel® SoC FPGA Embedded Design Suite, and the Cyclone V SoC Development Kit for Linux
A. Document Revision History of the Intel® FPGA SDK for OpenCL™ Standard Edition Cyclone® V SoC Getting Started Guide

2.10.3. Output from Successful Kernel Execution on the Cyclone V SoC Development Kit

When you run the host application to execute your OpenCL™ kernel on the Cyclone® V SoC Development Kit, the software notifies you of a successful kernel execution.

Example output: 

Reprogramming device [0] with handle 1
Querying platform for info:
==========================
CL_PLATFORM_NAME                         = Intel(R) FPGA SDK for OpenCL(TM)
CL_PLATFORM_VENDOR                       = Intel Corporation
CL_PLATFORM_VERSION   = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), <version>

Querying device for info:
========================
CL_DEVICE_NAME                    = c5soc : Cyclone V SoC Development Kit
CL_DEVICE_VENDOR                        = Intel(R) Corporation
CL_DEVICE_VENDOR_ID                     = 4466
CL_DEVICE_VERSION     = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), <version>
CL_DRIVER_VERSION                       = <version>
CL_DEVICE_ADDRESS_BITS                  = 64
CL_DEVICE_AVAILABLE                     = true
CL_DEVICE_ENDIAN_LITTLE                 = true
CL_DEVICE_GLOBAL_MEM_CACHE_SIZE         = 32768
CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE     = 0
CL_DEVICE_GLOBAL_MEM_SIZE               = 2147483648
CL_DEVICE_IMAGE_SUPPORT                 = false
CL_DEVICE_LOCAL_MEM_SIZE                = 16384
CL_DEVICE_MAX_CLOCK_FREQUENCY           = 1000
CL_DEVICE_MAX_COMPUTE_UNITS             = 1
CL_DEVICE_MAX_CONSTANT_ARGS             = 8
CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE      = 3758096384
CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS      = 3
CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS      = 1024
CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE      = 128
CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR   = 4
CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT  = 2
CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT    = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG   = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT  = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0
Command queue out of order?             = false
Command queue profiling enabled?        = true

Kernel initialization is complete.
Launching the kernel...

Thread #2: Hello from the Intel(R) FPGA SDK for OpenCL(TM) Compiler!

Kernel execution is complete.
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