50G Interlaken Design Example User Guide

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ID 683029
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 50G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 50G Interlaken Design Example User Guide

1.4. Simulating the Design

Figure 6. Procedure
Follow these steps to simulate the testbench:
  1. Change to the testbench simulation directory <example_design_install_dir>/example_design_a10/testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete. Refer to the table Steps to Run Simulation.
  3. Analyze the results.
    Table 1.  Steps to Run Simulation
    Simulator Instructions
    ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type 
    vsim -do vlog_pro.do
    If you prefer to simulate without bringing up the GUI, type 
    vsim -c -do vlog_pro.do
    VCS* In the command line, type sh vcstest.sh
    Xcelium* In the command line, type sh xcelium.sh
A successful simulation ends with the following message: 
Test PASSED
Level Two Title