50G Interlaken Design Example User Guide

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ID 683029
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 50G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 50G Interlaken Design Example User Guide

A. Document Revision History for 50G Interlaken Design Example User Guide

Date Changes
2022.10.31 Added support for the Xcelium* simulator.
2021.10.04 Updated simulator information in section: Simulating the Design and Hardware and Software Requirements.
2018.03.22 Made following changes to Simulating the Design section:
  • Corrected simulation directory location.
  • Updated command to simulate the testbench in NCSim and VCS simulators.
  • Updated simulation ends display message.
2016.10.31
  • Changed the title to 50G Interlaken Design Example User Guide.
  • Corrected the Figure: Arria 10 50G Interlaken IP Core Example Design Block Diagram.
  • Updated the Figure: Directory Structure for the Generated Example Design.
2016.05.02 Initial release
Level Two Title