50G Interlaken Design Example User Guide

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ID 683029
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 50G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 50G Interlaken Design Example User Guide

1.3. Generating the Design

Figure 4. Procedure
Follow these steps to generate the Intel® Arria® 10 hardware example design and testbench:
  1. In the IP Catalog (Tools > IP Catalog), select the Intel® Arria® 10 target device family.
    Note:

    The Quick Start hardware example design is only supported in Intel® Arria® 10 devices. The testbench is available for variations that target Intel® Arria® 10 devices or Stratix® V devices.

  2. In the IP Catalog, locate and double-click 50G Interlaken . The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys.
  4. You must select a specific Intel® Arria® 10 device in the Device field, or keep the default Intel® Quartus® Prime software device selection.
  5. Click OK. The parameter editor appears.
    Figure 5.  50G Interlaken Parameter Editor
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware example design.
    Note:

    At least one of the Simulation and Synthesis check boxes from Example Design Files must be selected to allow generation of Example Design Files.

  8. For Generated HDL Format, only Verilog is available.
  9. For Target Development Kit select the Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit. If you select a development kit, then the target device (selected in step 4) for Example Design is changed to match the device on target board.
  10. Click the Generate Example Design button.
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