2.5. Interface Signals
Port Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
clk50 | Input |
1 |
System clock input. Clock frequency must be 50 MHz. |
pll_ref_clk | Input |
1 |
Transceiver reference clock. Drives the RX CDR PLL. |
rx_pin | Input |
Number of lanes |
Receiver SERDES data pin. |
tx_pin | Output |
Number of lanes |
Transmit SERDES data pin. |
sys_pll_reset_n | Input | 1 | System reset. |