F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 1/07/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

7.13.3. TX 1-Step Timestamp Interface

When transmitting a 1-step PTP packet, the IP core modifies the PTP field on-the-fly. The IP core can change the UDP checksum or add extension bytes to adjust it. PTP headers can be part of the VLAN packets and can be encapsulated by UDP datagrams inside of the IPv4 and IPv6 packets.
Figure 51. Example of Ethernet Packet with a PTP HeaderThe figure depicts an Ethernet packet with PTP header embedded as an Ethernet payload in a simple non-VLAN packet.

The figure below shows how the PTP 1-step interface writes a 1-step timestamp to a PTP header. The timestamp signals are valid when i_tx_valid and i_tx_startofpacket signals are high. To initiate a timestamp request, the i_ptp_ins_ets signal must be high.

The PTP header must provide the offset of the starting octet of the timestamp field, compared to the first byte of the frame, as the i_ptp_ts_offset signal.
  • In above diagram, first byte of timestamp field is 48th byte, the byte offset (i_ptp_tx_offset) is 47.
  • The timestamp must not overwrite other fields such as headers or packet CRCs.
Figure 52. Using the IEEE 1588 TX 1-Step Timestamp Interface The figure depicts writing a 1-step timestamp to a PTP header. The actual timestamp offset for this packet is 48 octets. Offset of the correction field starting octet is 22 octets.
Table 57.  Signals of the 1-Step TX Timestamp InterfaceAll interface signals are clocked by i_clk_tx clock. The timestamp is always in 1588 v2 format.

Signal Name

Width

Description

i_ptp_ins_ets

i_ptp_ins_ets[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Insert an egress timestamp signal for the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_its_ets[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_ins_ets[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_ins_ets[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.
  • Must not use when i_ptp_ins_cf = 1. You cannot update residence time and insert an egress timestamp on the same packet.
  • Set the PTP timestamp field in the TX packet (i_ptp_ts_offset) to the byte position of the start of the timestamp field in the PTP header.
  • Set the PTP correction field in the TX packet (i_ptp_cf_offset) to the byte position of the start of the correction field in the PTP header.

i_ptp_ins_cf

i_ptp_ins_cf[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Update the correction field with residence time in the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_ins_cf[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_ins_cf[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_ins_cf[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.
  • Do not use when the egress timestamp signal (i_ptp_ins_ets) is asserted. You cannot update residence time and insert an egress timestamp on the same packet.
  • To calculate the residence time, use the i_ptp_tx_its signal to provide IP core with the ingress timestamp of the current packet when it entered the system.
  • Set the position of the PTP correction field in the TX packet (i_ptp_cf_offset) to the byte position of the start of the correction field in the PTP header.

i_ptp_zero_csum

i_ptp_zero_csum[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Overwrites the UDP checksum with zeros in the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_zero_csum[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_zero_csum[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_zero_csum[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.
  • Do not use when the update extended bytes field signal (i_ptp_update_eb) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet.
  • Set the position of the UDP checksum field in the TX packet (i_ptp_csum_offset) to the byte position of the start of the UDP checksum in the TX packet.

i_ptp_update_eb

i_ptp_update_eb[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Update the extended bytes field to cancel out checksum changes in the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.

When asserted, overwrites the extended bytes field in an IPv6 packet carried inside the current TX packet with a value that cancels out changes to the checksum due to changes to the UDP packet.

  • For TX MAC Avalon ST client interface, i_ptp_update_eb[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_update_eb[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_update_eb[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.
  • Do not use when the overwrite a UDP checksum with zeros signal (i_ptp_zero_csum) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet.
  • You do not have to provide the byte position of the start of the UDP extension field in the TX packet. The IP core assumes that the byte position starts two bytes before the CRC field.

i_ptp_p2p

i_ptp_p2p[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Add peer-to-peer mean path delay to correction field for the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_p2p[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_p2p[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_p2p[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.

i_ptp_asym

i_ptp_asym[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Add asymmetric latency to the correction field for the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_asym[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_asym[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_asym[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • Must not use when i_tx_skip_crc = 1. To recalculate the CRC for the TX packet, the TX skip CRC signal must be 0.

i_ptp_asym_sign

i_ptp_asym_sign[1:0]

1 bit (10GE/25GE,50GE/100GE/200GE)

2 bits (400GE)

 Sign of an asymmetry delay added to the correction field for the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • 0: Asymmetry delay is a positive value.
  • 1: Asymmetry delay is a negative value.
  • For TX MAC Avalon ST client interface, i_ptp_asym_sign[0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_asym_sign[0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_asym_sign[1] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

i_ptp_asym_p2p_idx[6:0]

i_ptp_asym_p2p_idx[13:0]

7 bits (10GE/25GE,50GE/100GE/200GE)

14 bits (400GE)

 Index of asymmetry delay and peer-to-peer mean path delay in the configurable lookup table 18 when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_asym_p2p_idx[6:0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_asym_p2p_idx[6:0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_asym_p2p_idx[13:7] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

i_ptp_ts_offset[15:0]

i_ptp_ts_offset[31:0]

16 bits (10GE/25GE,50GE/100GE/200GE)

32 bits (400GE)

 Presents the position of the PTP timestamp field in the TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_ts_offset[15:0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_ts_offset[15:0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_ts_offset[31:16] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
  • The PTP timestamp field is 10 octets long, starting from the position given by the offset. PTP adds the lower 16 bits of the 96-bit timestamp in the lower 2 octets of the correction field.
    CAUTION:
    You must set the offset to a position within the TX packet, or the PTP insertion operation fails. Also, you must not overlap the PTP fields.

i_ptp_cf_offset[15:0]

i_ptp_cf_offset[31:0]

16 bits (10GE/25GE,50GE/100GE/200GE)

32 bits (400GE)

 Presents the position of the PTP correction field in the TX packet when Ethernet rate is 10GE/25GE,50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_cf_offset[15:0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_cf_offset[15:0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_cf_offset[31:16] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
  • The PTP correction field is 8 octets long, starting from the position given by the offset. PTP adds the lower 16 bits of the 96-bit timestamp in the lower 2 octets of the correction field..
    CAUTION:
    You must set the offset to a position within the TX packet, or the PTP insertion operation fails. Also, you must not overlap the PTP fields.

i_ptp_csum_offset[15:0]

i_ptp_csum_offset[31:0]

16 bits (10GE/25GE,50GE/100GE/200GE)

32 bits (400GE)

 Position of the UDP checksum field in the TX packet when Ethernet rate is 10GE/25GE,50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_csum_offset[15:0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_csum_offset[15:0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_csum_offset[31:16] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
    CAUTION:
    You must set the offset to a position within the TX packet, or the PTP insertion operation fails. Also, you must not overlap the PTP fields.

i_ptp_tx_its[95:0]

i_ptp_tx_its[191:0]

96 bits (10GE/25GE,50GE/100GE/200GE)

192 bits (400GE)

 Presents the ingress timestamp for the TX packet residence time calculation when Ethernet rate is 10GE/25GE,50GE/100GE/200GE/400GE.

The timestamp represents time when packet arrives in the system. To generate the residence time, the TX packet compares this timestamp to the time when packet left the system.

  • For TX MAC Avalon ST client interface, i_ptp_tx_its[95:0] is valid only when both TX valid (i_tx_valid) and TX SOP (i_tx_startofpacket) signals are asserted.
  • For TX MAC segmented client interface, i_ptp_tx_its[95:0] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_tx_its[191:96] is valid only when TX valid (i_tx_mac_valid) is asserted and i_tx_mac_inframe[15:8] contains the SOP.

  • The residence time value updated in the correction field is not valid if TX egress timestamp is larger than the TX ingress timestamp by 4 seconds.
18 The lookup table is accessible via the PTP tile adapter module's Avalon® memory-mapped interface. For more information, refer to PTP Asymmetry Delay Reconfiguration Interface and PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface.
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