F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 1/07/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

5.6. Custom Cadence

You can use custom cadence to ensure that the TX PMA interface FIFO doesn’t overflow due to the over clocking of the datapath. You must use the custom cadence in the following 2 scenarios:
  • When the reference clock for TX PMA and the reference clock for system PLL are different. Although, system PLL frequency is configured to be same as PMA parallel frequency, there might be PPM differences between TX PMA parallel clock frequency and system PLL frequency.
  • When the system PLL frequency is more than the PMA parallel clock frequency. This non-standard system PLL frequency may require when several interfaces share the same system clock ( some interfaces need to run at over-clocked system PLL frequency greater than PMA parallel clock frequency). This scenario may occur due to a limited number of system PLLs or when dynamic reconfiguration is enabled.

If your interface requires custom cadence, you must enable custom cadence. To enable custom cadence, select System PLL frequency IP parameter to Custom and input your required custom system PLL frequency.

When System PLL frequency IP parameter is set to Custom, the IP internally includes a custom cadence controller.

If you require an external custom cadence controller instead, you must enable it by selecting External Custom Cadence Controller IP parameter. When selected, this option enables the external custom cadence controller and i_custom_cadence input port becomes available in the IP port list. You must drive the i_custom_cadence input port producing a steady data valid cadence.

In multiple IP instance designs, you may use the external custom cadence controller option to share the logic with multiple IPs and reduce the resource utilization.

Table 26.  Custom Cadence Use Cases
Abbreviations:
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL91: IEEE 802.3 RS(528,514) (CL91)
  • CL134: IEEE 802.3 RS(544,514) (CL134)
  • ETC: Ethernet Technology Consortium ETC RS(272, 258)
  • MAC AvST: MAC Avalon® ST
  • MAC Seg: MAC Segmented
Configuration System PLL frequency (in MHz) Use Case Custom Cadence Controller Selection
NRZ modes
  • with FEC mode:
    • None
    • CL74
    • CL91
  • with client interface:
    • MAC Seg
    • MAC AvST
 830.078125
  • If system PLL is shared with FEC mode configuration CL134 or ETC and system PLL reference clock and PMA reference clock sources are same and use the same clock frequency (0 ppm).
  • If system PLL reference clock and PMA reference clock sources are different, enable Custom system PLL Frequency and set the input to 830.078125 MHz.

The IP enables internal custom cadence controller logic when 830.078125 MHz is selected instead of typical 805.6640625 MHz.

PCS

OTN

FlexE

805.6640625

or

830.078125
  • If system PLL reference clock and PMA reference clock sources are same and use the same clock frequency (0 ppm).
  • If system PLL reference clock and PMA reference clock sources are different, enable Custom system PLL Frequency and set the input to 805.6640625 or 830.078125 MHz.

The IP enables internal custom cadence controller logic when 830.078125 or 805.6640625 MHz.

Any variant with client interface:
  • MAC Seg
  • MAC AvST
  • MII PCS only
  • PCS66 OTN
  • PCS66 FlexE
 Custom PLL
  • Requires a non-standard system PLL frequency, for example 900 MHz.
  • System PLL reference clock and PMA reference clock sources are different.
The IP enables internal custom cadence controller when the external custom cadence controller is disabled.

When the external custom cadence controller is enabled, you must drive the i_custom_cadence port.

Table 27.  Various Custom Cadence Scenarios for 25GE-1 with IEEE 802.3 RS(528,514) (CL91) FEC ModeThe example assumes system PLL frequency of 805.6640625 MHz.
Client Interface System PLL Frequency (in MHz) PMA/System PLL Reference Clock Source Custom Cadence Required Custom Cadence Controller Client Interface Frequency FIFO Requirement
MAC Avalon® ST 805.6640625 Same No — Same as system PLL frequency/2

(402.83203125 MHz)

 No
MAC Avalon® ST 805.6640625 Same No — Different as system PLL frequency/2

(For example, 390.625 MHz)

Enable asynchronous adapter clocks parameter is On
MAC Avalon® ST Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

402.83203125 MHz)

 No
MAC Avalon® ST Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example, 390.625 MHz)

Enable asynchronous adapter clocks parameter is On 17
MAC Avalon® ST 830.078125 Same Yes Internal Same as system PLL frequency/2

(415.078125 MHz)

 No
MAC Avalon® ST 830.078125 Same Yes Internal Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

 Enable asynchronous adapter clocks parameter is On
MAC Avalon® ST Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

415.078125 MHz/450 MHz)

 No
MAC Avalon® ST Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

 Enable asynchronous adapter clocks parameter is On17
MAC segmented 805.6640625 Same No — Same as system PLL frequency/2

(402.83203125 MHz)

 No
MAC segmented 805.6640625 Same No — Different as system PLL frequency/2

(For example, 390.625 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

402.83203125 MHz)

 No
MAC segmented Custom

(For example, 805.6640625)

Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example, 390.625 MHz)

Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented 830.078125 Same Yes Internal Same as system PLL frequency/2

(415.078125 MHz)

 No
MAC segmented 830.078125 Same Yes Internal Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

 Client Custom FIFO instantiated outside of the Ethernet IP
MAC segmented Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Same as system PLL frequency/2

(For example,

415.078125 MHz/450 MHz)

 No
MAC segmented Custom

(For example, 830.078125 or 900)

Same or Different (PPM) Yes Internal or External Different as system PLL frequency/2

(For example,

390.625 MHz/402.83203125 MHz)

 Client Custom FIFO instantiated outside of the Ethernet IP
17 When using multiple IP instances, if both Enable asynchronous adapter clocks and External Custom Cadence Controller are enabled, you must generate each IP's i_custom_cadence signal using corresponding o_clk_pll clock.
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