Visible to Intel only — GUID: GUID-5C92D652-B070-4A8B-95A3-6A9CE89EF802
Why is FPGA Compilation Different?
Types of SYCL* FPGA Compilation
FPGA Compilation Flags
Other SYCL* FPGA Flags Supported by the Compiler
Emulate and Debug Your Design
Evaluate Your Kernel Through Simulation
Device Selectors for FPGA
FPGA IP Authoring Flow
Fast Recompile for FPGA
Generate Multiple FPGA Images (Linux only)
FPGA BSPs and Boards
Targeting Multiple Homogeneous FPGA Devices
Targeting Multiple Platforms
FPGA-CPU Interaction
FPGA Performance Optimization
Use of RTL Libraries for FPGA
Use SYCL Shared Library With Third-Party Applications
FPGA Workflows in IDEs
Intel oneAPI DPC++ Library (oneDPL)
Intel oneAPI Math Kernel Library (oneMKL)
Intel oneAPI Threading Building Blocks (oneTBB)
Intel oneAPI Data Analytics Library (oneDAL)
Intel oneAPI Collective Communications Library (oneCCL)
Intel oneAPI Deep Neural Network Library (oneDNN)
Intel oneAPI Video Processing Library (oneVPL)
Other Libraries
Visible to Intel only — GUID: GUID-5C92D652-B070-4A8B-95A3-6A9CE89EF802
FPGA Compilation Flags
FPGA compilation flags control the FPGA image type the Intel® oneAPI DPC++/C++ Compiler targets.
The following are examples of Intel® oneAPI DPC++/C++ Compiler commands that target the FPGA image types:
# FPGA emulator image
icpx -fsycl -fintelfpga fpga_compile.cpp -o fpga_compile.fpga_emu
# FPGA simulator image: FPGA device family
# Note that in this release, you can target Intel Agilex® 7 devices in any of the following formats:
# -Xstarget=Agilex | -Xstarget=Agilex7 | -Xstarget="Agilex 7" | -Xstarget=agilex7 | -Xstarget="agilex 7" |
# The following command is an example that shows one of the supported formats:
icpx -fsycl -fintelfpga fpga_compile.cpp -Xssimulation -Xstarget=Agilex7 -Xsghdl -o fpga_compile.fpga_sim
# FPGA simulator image: FPGA part number
icpx -fsycl -fintelfpga fpga_compile.cpp -Xssimulation -Xstarget=AGFB014R24A3EV -Xsghdl -o fpga_compile.fpga_sim
# FPGA simulator image: explicit board
icpx -fsycl -fintelfpga fpga_compile.cpp -Xssimulation -Xstarget=intel_s10sx_pac:pac_s10 -o fpga_compile.fpga_sim
# FPGA early image (with optimization report): FPGA device family
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -fsycl-link=early -Xstarget=Stratix10 -o fpga_compile_report.a
# FPGA early image (with optimization report): FPGA part number
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -fsycl-link=early -Xstarget=1SG280LU3FS0E3VG -o fpga_compile_report.a
# FPGA early image (with optimization report): default board
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -fsycl-link=early -o fpga_compile_report.a
# FPGA early image (with optimization report): explicit board
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -fsycl-link=early -Xstarget=intel_s10sx_pac:pac_s10 -o fpga_compile_report.a
# FPGA hardware image: FPGA device family
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -Xstarget=Arria10 -o fpga_compile.fpga
# FPGA hardware image: FPGA part number
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -Xstarget=10AX115S2F45I1SG -o fpga_compile.fpga
# FPGA hardware image: default board
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -o fpga_compile.fpga
# FPGA hardware image: explicit board
icpx -fsycl -fintelfpga fpga_compile.cpp -Xshardware -Xstarget=intel_s10sx_pac:pac_s10 -o fpga_compile.fpga
NOTE:
When you specify -o flag, the output directory is named based on what you specify with the -o flag. For example, if you specify -o fpga_compile.fpga, the output directory would be fpga_compile.prj. However, when you do not specify the -o flag, the output directory is always a.prj.
The following table explains the compiler flags used in the above example commands:
Flag |
Explanation |
|---|---|
-fintelfpga |
Performs ahead-of-time (offline) compilation for FPGA. |
-Xshardware |
Instructs the compiler to target FPGA hardware. If you omit this flag, the compiler targets the FPGA emulator.
NOTE:
Using the prefix -Xs causes an argument to be passed to the FPGA backend.
|
-Xsemulator |
Generates an emulator device image. This is the default behavior. |
-Xssimulation |
Generates a simulator device image. |
-fsycl-link=early |
Instructs the compiler to stop after creating the FPGA early image (and associated optimization report). |
-Xstarget=<FPGA device family> -Xstarget=<FPGA part number> -Xstarget=<bsp:variant> |
[Optional] Instructs the compiler to target an FPGA device family, an FPGA part number, or an FPGA board as follows:
If you omit the -Xstarget flag, the compiler chooses the default FPGA board variant pac_a10 from the intel_a10gx_pac BSP (equivalent to -Xstarget=intel_a10gx_pac:pac_a10). |
WARNING:
The output of an icpx compile command overwrites the output of previous compiles that used the same output name. Therefore, Intel® recommends using unique output names (specified with -o). This is especially important for FPGA compilation since a lost hardware image may take hours to regenerate.
In addition to the compiler flags demonstrated by the commands above, there are flags to control the verbosity of the icpx command’s output, the number of parallel threads to use during compilation, and so on. The following section briefly describes those flags.
Other SYCL* FPGA Flags Supported by the Compiler
The Intel® oneAPI DPC++/C++ Compiler offers several options that allow you to customize the kernel compilation process. The following table summarizes other options supported by the compiler:
Option name |
Description |
|---|---|
-fsycl-help=fpga |
Prints out FPGA-specific options for the icpx command. |
-fsycl-link=early -fsycl-link=image |
|
-reuse-exe=<exe_file> |
Instructs the compiler to extract the compiled FPGA hardware or simulation image from the existing executable if the kernel has not changed and package it into the new executable, saving the device or simulation compilation time. This option is not applicable when compiling for emulation. Refer to the Fast Recompile for FPGA section for additional information. |
-Xsv |
FPGA backend generates a verbose output describing the progress of the compilation. |
-Xsghdl[=<depth>] |
Causes the simulation flow to log signals to Siemens EDA (formerly Mentor Graphics) Questa* waveform files. Use the optional <depth> attribute to specify how many levels of hierarchy are logged. If you do not specify a value for the <depth> attribute, a depth of 1 is used by default. |
-Xsparallel=<num_threads> |
Sets the degree of parallelism used in the FPGA bitstream compilation. The <num_threads> value specifies the number of parallel threads you want to use. The maximum recommended value is the number of available cores. Setting this flag is optional. The default behavior is for the Intel® Quartus® Prime software to compile in parallel on all available cores. |
-Xsseed=<value> |
Sets the seed used by Intel® Quartus® Prime software when generating the FPGA bitstream. The value must be an unsigned integer, and by default, the value is 1. |
-Xsfast-compile |
Runs FPGA bitstream compilation with reduced effort. This option allows faster compile time but at the cost of reduced performance of the compiled FPGA hardware image. Use this flag only for faster development time. It is not intended for production-quality results. The -Xsfast-compile flag sets the Intel Quartus Prime Pro Edition software into the compile mode that is dominated by the Fast Functional Test.
WARNING:
When compiling your SYCL kernel using the -Xsfast-compile flag, you might see functional failures due to timing violations in your design. In such cases, either avoid using the -Xsfast-compile flag or try compiling your kernel with different seeds.
|
For more information about FPGA optimization flags, refer to the Optimization Flags section in the FPGA Optimization Guide for Intel® oneAPI Toolkits.