Visible to Intel only — GUID: GUID-B20C944D-CD8A-4126-8F89-708057EEFAC0
Visible to Intel only — GUID: GUID-B20C944D-CD8A-4126-8F89-708057EEFAC0
Terminology
Term |
Abbreviation |
Definition |
Blitter |
BLT |
Block Image Transferrer |
Child Thread |
A branch-node or a leaf-node thread that is created by another thread. It is a kind of thread associated with the media fixed function pipeline. A child thread is originated from a thread (the parent) executing on a VE and forwarded to the Thread Dispatcher by the TS unit. A child thread may or may not have child threads depending on whether it is a branch-node or a leaf-node thread. All pre-allocated resources such as URB and scratch memory for a child thread are managed by its parent thread. See also Parent Thread. |
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Command |
Directive fetched from a ring buffer in memory by the Command Streamer and routed down a pipeline. Should not be confused with instructions which are fetched by the instruction cache subsystem and executed on a VE. |
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Command Streamer |
CS or CSI |
Functional unit of the Graphics Processing Engine that fetches commands, parses them, and routes them to the appropriate pipeline. |
Core |
Alternative name for a VE in the multi-processor system. See EU. |
|
Dual Sub-slice |
DSS |
The collection of Vector Engines (VE) or Execution Units (EU) that have a common set of shared function units, such as sampler, dataport, and pixel port. |
End of Thread |
EOT |
A message sideband signal on the Output message bus signifying that the message requester thread is terminated. A thread must have at least one SEND instruction with the EOT bit in the message descriptor field set to properly terminate. |
Exception |
Type of (normally rare) interruption to VE/EU execution of a thread’s instructions. An exception occurrence causes the VE/EU thread to begin executing the System Routine, which is designed to handle exceptions. |
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Execution Channel |
Single lane of a SIMD operand. |
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Execution Size |
ExecSize |
Execution Size indicates the number of data elements processed by an SIMD instruction. It is one of the instruction fields and can be changed per instruction. |
Execution Unit |
EU |
An EU is a multi-threaded processor within the multi-processor system. Each EU is a fully-capable processor containing instruction fetch and decode, register files, source operand swizzle and SIMD ALU, etc. An EU is also referred to as a Core. |
Execution Unit Identifier |
EUID |
A 4-bit field within a thread state register (SR0) that identifies the row and column location of the EU where a thread is located. A thread can be uniquely identified by the EUID and TID. |
Execution Width |
ExecWidth |
The width of each of several data elements that may be processed by a single SIMD instruction. |
General Register File |
GRF |
Large read/write register file shared by all the EUs/VEs for operand sources and destinations. This is the most commonly used read-write register space organized as an array of 256-bit registers for a thread. |
General State Base Address |
The Graphics Address of a block of memory-resident “state data”, which includes state blocks, scratch space, constant buffers, and kernel programs. The contents of this memory block are referenced via offsets from the contents of the General State Base Address register. See Graphics Processing Engine. |
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Graphics Processing Engine |
GPE |
Collective name for the Subsystem, the 3D and Media pipelines, and the Command Streamer. |
Memory-Mapped Input/Output |
MMIO |
A method for performing input/output between the CPU/GPU and peripheral devices. |
Message |
Messages are data packages transmitted from a thread to another thread, another shared function, or another fixed function. Message passing is the primary communication mechanism of Intel GPU architecture. |
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Parent Thread |
A thread corresponding to a root-node or a branch-node in thread generation hierarchy. A parent thread may be a root thread or a child thread depending on its position in the thread generation hierarchy. | |
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Resource Streamer |
RS |
Functional unit of the Graphics Processing Engine that examines the commands in the ring buffer in an attempt to pre-process certain long latency items for the remainder of the graphics processing. |
Root Thread |
A root-node thread. A thread corresponds to a root-node in a thread generation hierarchy. It is a kind of thread associated with the media fixed function pipeline. A root thread is originated from the VFE unit and forwarded to the Thread Dispatcher by the TS unit. A root thread may or may not have child threads. A root thread may have scratch memory managed by TS. A root thread with children has its URB resource managed by the VFE. |
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Single Instruction Multiple Data |
SIMD |
A parallel processing architecture that exploits data parallelism at the instruction level. It can also be used to describe the instructions in such an architecture or to describe the amount of data parallelism in a particular instruction (SIMD8 for example). |
Spawn |
To initiate a thread for execution on an EU/VE. Done by the thread spawner as well as most FF units in the 3D Pipeline. |
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Sub-Register |
Subfield of a SIMD register. A SIMD register is an aligned fixed size register for a register file or a register type. For example, a GRF register, r2, is a 256-bits wide, 256-bit aligned register. A sub-register, r2.3:d, is the fourth dword of GRF register r2. |
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Subsystem |
The name given to the resources shared by the FF units, including shared functions and EUs/VEs. |
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Surface |
A rendering operand or destination, including textures, buffers, and render targets. |
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Surface State |
State associated with a render surface. |
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Surface State Base Pointer |
Base address used when referencing binding table and surface state data. |
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Synchronized Root Thread |
A root thread that is dispatched by TS upon a ‘dispatch root thread’ message. |
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System IP |
SIP |
There is one global System IP register for all the threads. From a thread’s point of view, this is a virtual read only register. Upon an exception, hardware performs some bookkeeping and then jumps to SIP. |
System Routine |
Sequence of instructions that handles exceptions. SIP is programmed to point to this routine, and all threads encountering an exception will call it. |
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Thread |
An instance of a kernel program executed on an EU/VE. The life cycle for a thread starts from the executing the first instruction after being dispatched from Thread Dispatcher to an EU/VE to the execution of the last instruction - a send instruction with EOT that signals the thread termination. Threads in the system may be independent from each other or communicate with each other through Message Gateway share function. |
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Thread Dispatcher |
TD, TDL |
Functional unit that arbitrates thread initiation requests from Fixed Functions units and instantiates the threads on EUs/VEs. |
Thread Identifier |
TID |
The field within a thread state register (SR0) that identifies which thread slots on an EU/VE a thread occupies. A thread can be uniquely identified by the EUID and TID. |
Thread Payload |
Before a thread starting execution, some amount of data is pre-loaded into the thread’s GRF (starting at r0). This data is typically a combination of control information provided by the spawning entity (FF Unit) and data read from the URB. |
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Thread Spawner |
TS |
The second and the last fixed function stage of the media pipeline that initiates new threads on behalf of generic/media processing. |
Unsynchronized Root Thread |
A root thread that is automatically dispatched by TS. |