Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 5/08/2024
Public
Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

For the latest and previous versions of this user guide, refer to Migrating OpenCL FPGA Designs to SYCL*. If a software version is not listed, the user guide for the previous software version applies.

Document Revision History
Date Release Version Changes
May 2024 2024.1
  • Fix broken links
March 2024 2024.1
  • Maintenance release.
November 2023 2024.0
  • Maintenance release.
July 2023 2023.2
  • Maintenance release.
March 2023 2023.1
  • Maintenance release.
Level Two Title