Developer Reference

Migrating OpenCL™ FPGA Designs to SYCL*

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ID 767849
Date 5/08/2024
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Document Table of Contents
Document Table of Contents x
Migrating OpenCL™ FPGA Designs to SYCL* FPGA Design Flow Modify Your Design Flags, Attributes, Directives, and Extensions Histogram Design Example Walkthrough Additional Information Document Revision History for Migrating OpenCL FPGA Designs to SYCL*
Migrating OpenCL™ FPGA Designs to SYCL* x
Overview Prerequisites
Modify Your Design x
Basic Modifications Advanced Modifications
Basic Modifications x
Host Code Modification Device Code Modification
Advanced Modifications x
Host Code Modification Device Code Modification
Device Code Modification x
C++ Features in Device Code
Flags, Attributes, Directives, and Extensions x
General Information Flags FPGA Board-Specific Flags Compiler Flags Optimization Flags Memory Attributes Loop Directives Floating Point Optimizations Kernel Attributes Intra-kernel Registered Assignment Function Channels/Pipes APIs LSU Attributes
Histogram Design Example Walkthrough x
OpenCL Sample Code SYCL Sample Code SYCL Sample Code With Explicit Data Movement
Document Revision History for Migrating OpenCL FPGA Designs to SYCL* x
Notices and Disclaimers
Migrating OpenCL™ FPGA Designs to SYCL*
FPGA Design Flow
Modify Your Design
Flags, Attributes, Directives, and Extensions
Histogram Design Example Walkthrough
Additional Information
Document Revision History for Migrating OpenCL FPGA Designs to SYCL*

Compiler Flags

The following table lists the compiler flags in OpenCL and their closely related or equivalent flags in SYCL*:

OpenCL SYCL Description
-c -c Compiles your kernel and generates the output of the parser without creating an FPGA programming image file.
-rtl -fsycl-link=early Instructs the compiler to stop after creating the FPGA early image and the associated optimization report.
-I=<directory> -I=<directory>

Adds a directory to the list of directories that the compiler searches for header files during kernel compilation.

-o <file_name> -o <file_name>

In OpenCL, specifies the name of the output .aocr or .aocx file.

In SYCL, specifies the output executable name.

-board=<board_name>-board-package=<board_package_path> -Xstarget=<BSP>:<fpga_board_variant> In SYCL, it specifies the FPGA target and variant. If omitted, the compiler chooses the default FPGA target and variant, which are installation dependent. Refer to the FPGA BSPs and Boards section in the Intel® oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for additional details.
-high-effort -Xsseed=<n>

The -high-effort flag in OpenCL simply reruns the Intel® Quartus® Prime software compilation up to three times with different seeds to fit the design and meet timing. In SYCL, use the -Xsseed=<n> option to change the seed and run multiple compiles yourself while changing the seed value (n) for each compile. To see if the design fits and meets timing, you can check the error code of the icpx command. If it returns error code 42, the design failed to fit or meet timing. If it returns 0, it passed. See -Xsseed=<value> below for more information.

-seed=<value> -Xsseed=<value>

Sets the seed used by the Intel® Quartus® Prime software when generating the FPGA bitstream. The value must be an unsigned integer, and by default, the value is 1.

-D<macro_name> -D<macro_name> Defines a preprocessor macro named macro_name.
-v -Xsv FPGA backend generates a verbose output describing the progress of the compilation.
-report -Xsreport Prints area estimates on the screen after initial compilation.
-W -w Suppresses all warning messages.
-Werror -Werror Converts all warning messages into error messages.
-g0 -g0

Removes source information from the compiler reports and source code and customer IP information from the .aocx file or SYCL executable.

-fast-compile -Xsfast-compile Runs FPGA bitstream compilation with reduced effort. This option allows faster compile time but at the cost of reduced performance of the compiled FPGA hardware image. Use this flag only for faster development time. It is not intended for production-quality results.
Not supported -reuse-exe

Instructs the compiler to extract the compiled FPGA hardware image from the existing executable and package it into the new executable, saving the device compilation time. This option is helpful only when compiling for hardware.

Refer to the Separating Device and Host Code Compilation section in the Intel oneAPI DPC++/C++ Compiler Handbook for Intel FPGAs for additional information.

-incremental Not supported In OpenCL, this flag compiles the modifications you make to your OpenCL design incrementally.
-ecc Not supported Enables error-correction coding on the kernel memories (that is, M20ks and MLABs).
-march=emulator -Xsemulator Generates an emulator device image. This is the default behavior for SYCL.
-march=simulator -Xssimulation Compiles a kernel for simulation.
-parallel=<num_threads> -Xsparallel=<num_threads>

Sets the degree of parallelism used in the FPGA bitstream compilation.

The <num_threads> value specifies the number of parallel threads you want to use. The maximum recommended value is the number of available cores. Setting this flag is optional. The default behavior is for the Quartus® Prime software to compile in parallel on all available cores.

-profile -Xsprofile Instruments the kernel pipeline with performance counters.
-profile-shared-counters -Xsprofile-shared-counters Turns on the shared performance counters profiling mode when used with the -Xsprofile flag during compilation.
Parent topic: Flags, Attributes, Directives, and Extensions
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