DPCT1078

Intel® DPC++ Compatibility Tool Developer Guide and Reference

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ID 768918

Date 10/31/2024

Version

Public

Visible to Intel only — GUID: GUID-A39BA2AA-83E4-4C8E-94F4-66795AACF69B

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DPCT1078

Message

Consider replacing memory_order::acq_rel with memory_order::seq_cst for correctness if strong memory order restrictions are needed.

Detailed Help

memory_order::acq_rel is a light-weight fence that is sufficient for memory synchronization in most programs. If a program needs total sequentially consistent memory order to ensure correctness, replace memory_order::acq_rel with memory_order::seq_cst.

Suggestions to Fix

Replace memory_order::acq_rel with memory_order::seq_cst if stricter memory order is needed.

For example, this original CUDA* code:

__device__ void foo_dev() {
  ...
  __threadfence();
  ...
}

results in the following migrated SYCL code:

void foo_dev() {
  ...
  /*
  DPCT1078:0: Consider replacing memory_order::acq_rel with
  memory_order::seq_cst for correctness if strong memory order restrictions are
  needed.
  */
  sycl::atomic_fence(sycl::memory_order::acq_rel, sycl::memory_scope::device);
  ...
}

which is rewritten to:

void foo_dev() {
  ...
  // Assuming strong memory order restrictions are need here
  sycl::atomic_fence(sycl::memory_order::seq_cst, sycl::memory_scope::device);
  ...
}

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DPCT1078

Message

Detailed Help

Suggestions to Fix