Nios® V Processor Developer Center

1. Prerequisites

Create My Intel® Account

• Create your Intel® account from the Register Intel® Account page.
• Your Intel account allows you to file service requests, register for training courses, download software, access resources, and more.

Design Considerations

Why choose the Nios V processor?

The Nios® V processor is designed for Intel® FPGA devices and developed based on RISC-V specification. For more information such as processor performance benchmark, please refer to Nios® V Processor Reference Manual.

Which Operating System (OS) should I choose?

Bare-Metal

Bare-metal is an application-based system without the support of any operating system.

The bare-metal approach offers:

• Absolute control of hardware
• Increased efficiency
• Minimal size (both flash and memory footprint)
• No dependency on other source codes or libraries
• Ease in validation and code coverage analysis.

You may also consider bare-metal development if you:

• Do not require multi-task or multi-thread operations
• Are performing board bring-up and need to focus on each peripheral individually
• Are re-using existing legacy code that is already developed as bare metal

To develop a bare-metal application for the Nios® V processor, you must be familiar with developing runtime capabilities to ensure that your application makes efficient use of the resources available in your CPU subsystem. Examples of what may be required are as follows:

• In-depth knowledge of the hardware platform
• Developing runtime capabilities to manage the process between the core and the cache subsystem if you want to fully utilize the CPU subsystem, as a typical bare-metal application uses only a single core
• Developing capabilities to manage and schedule processes, handle inter-process communications, and synchronize events within your application

If your scheduled project does not allow for the effort it may take to become familiar with the above points, then it is recommended that you consider using other alternatives.

Intel® Hardware Abstraction Layer (HAL) and Real Time Operating System (RTOS)

Considering the above statements, it often makes sense to use an abstraction layer or an operating system to realize the maximum performance from the Nios® V processor with minimal effort.

2. Getting Started

Select Target Board

We recommend starting your development on an Intel® FPGA development kit because the Nios® V processor design examples are targeted to run on those boards. Please refer to the Design Consideration section for supported Intel® FPGA devices.

Refer to Intel® FPGA Development Kits for a list of available boards.

Install Development Tools

You will need install the Quartus® Prime software and the Ashling* RiscFree* IDE for Intel FPGA to start developing a Nios® V processor system. Navigate to the FPGA Software Download Center to install the latest software version.

Create Your 1st Nios® V Processor System

The Nios® V Embedded Processor Design Handbook introduce you to the system development flow for the Nios® V processor. Together with the Quartus® Prime software and the Ashling* RiscFree* IDE for Intel® FPGA, you can build a complete solution comprising a hardware system design and a software program that runs on the Nios® V processor and interfaces with the components on the Intel® development boards.

3. Creating Your Own Project

Project Types

The Nios® V Processor Development Tools comprised of Board Support Package Editor and Ashling* RiscFree* IDE for Intel® FPGA to build Nios® processor-based projects. Nios® V supports two different types of projects GUI-Based and CLI-Based Projects.

Design Flow

The figure below illustrates the general Nios® V processor system development flow.

The Nios® V processor development flow consists of three elements as follows:

• System design, involving both hardware and software
• Hardware design
• Software design

You begin your Nios® V processor development by developing a system concept and performing a system requirements analysis. Next, you create and generate the system in the Platform Designer, and produce a Platform Designer file. The Platform Designer file includes Nios® V processor cores and standard components. After system generation, hardware and software flows can be initiated.

• For Nios® V processor hardware development, you must:
• Select the target FPGA based on system requirements. Refer to Design Considerations section.
• Integrate the Platform Designer system with the Quartus® Prime software project.
• Assign pin locations.
• Configure timing requirements and other design constraints.
• After compiling the hardware design, download the .sof file to the target board.

For Nios® V processor software development, you must:

• Develop your software with the Nios® V Processor Tools and Ashling* RiscFree* IDE for Intel® FPGA. The Nios® V processor software includes the HAL, peripheral drivers, user C/C++ application codes, and custom libraries.
• Download the .elf file to the Nios® V processor system on the target board after building the application and board support package (BSP). The Nios® V processor system is ready for testing and debugging.

If you find that your software does not meet specifications during the test, return to the beginning of the software flow and check the application codes, drivers, and BSP to correct any errors and ensure that the Nios® V processor system executes correctly.

If the hardware does not meet specifications, return to the Platform Designer system define and generation step, and restart both the hardware and software flow. The key file required to generate the application software is the Platform Designer system file. Because this file describes hardware components and connections, you must regenerate this file if you make a hardware change. The system is complete when both the software and hardware meet specifications.

4. Design Examples

There are plenty of design examples available to help you get started with Intel® FPGA products. All examples can be used as a starting point for your own designs, and they are customizable to implement other specific use cases.

The Nios® V Processor Intel FPGA IP offers a selection of simple design examples to begin your journey with Nios® V processor.

Detailed documentation can be found in “Nios® V Processor Design Example Scripts” from Nios® V Processor Software Development Handbook.

How to run a Nios® V processor “Hello World” application in Intel HAL, µC/OS-II RTOS, and FreeRTOS?

• Learn how to run a Nios® V processor “Hello World” application in Intel HAL, µC/OS-II RTOS, and FreeRTOS:
  • Documentation: Nios® V Processor Quick Start Guide
  • Design Examples: FPGA Design Store, Nios V, Hello World Design Examples

How to run a Nios® V processor “Hello World” application in Zephyr RTOS?

• Quick Start Guide on how to generate Zephyr Hello World application on Nios V Hello World design example.
• Nios® V/g
  • Documentation: Nios® V/g Zephyr Design Example - Hello World
  • Design Example: Arria® 10 FPGA - Nios® V/g Processor based Hello World
• Nios® V/m
  • Documentation: Nios® V/m Zephyr Design Example - Hello World
  • Design Example: Arria® 10 FPGA - Nios® V/m Processor based Hello World

How to run a Nios® V processor with MicroC/TCP-IP software package?

• Learn how to run a Nios® V processor with MicroC/TCP-IP software package, refer to the “Nios® V Processor - Using the Micro/TCP-IP Stack”.
  • Documentation: Nios® V Processor - Using the MicroC/TCP-IP Stack
  • Design Examples:
    • Arria® 10 FPGA - Simple Socket Server Design for Nios® V/m Processor
    • Arria® 10 FPGA - μC/OS-II RTOS with Iperf for Nios® V/m Processor

How to run a Nios® V processor with Remote System Update in SDM-based Devices?

• Learn how to run a Nios® V processor with Remote System Update in SDM-based Devices, refer to the “Nios® V Processor RSU Quick Start Guide in SDM-based Devices”.
  • Documentation and Design Example: Nios® V Processor RSU Quick Start Guide in SDM-based Devices

How to run a Nios® V processor with Custom Instruction?

• Learn how to run a Nios® V processor with Custom Instruction, refer to the “Nios® V Processor — Using Custom Instruction”.
  
  • Documentation: Nios® V Processor — Using Custom Instruction
  • Design Examples: 
    • Agilex™ 7 FPGA - Custom Instruction Design on Nios® V/g Processor
    • Agilex™ 7 FPGA - CRC Custom Instruction Design on Nios® V/g processor

5. Additional Resources