Arria® 10 FPGA – μC/OS-II* RTOS with IPerf for the Nios® V/m Processor Design Example

Arria® 10 FPGA – μC/OS-II* RTOS with IPerf for the Nios® V/m Processor Design Example

787050
9/14/2023
A newer version of this software is available, which includes functional and security updates. Customers should click here to update to the latest version.

Introduction

Perf 2 is a benchmarking tool for measuring performance between two systems, and it can be used as a server or a client.

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2
IP Cores (3)
IP Core IP Core Category
Nios V/m Processor Intel FPGA IP Embedded Processor
Triple-Speed Ethernet Intel FPGA IP Ethernet
altera_msgdma DMA

Detailed Description

An iPerf server receives an iPerf request sent over a TCP/IP connection from any iPerf clients and runs the iPerf test according to the provided arguments. Each test reports the bandwidth, loss, and other parameters.



Please refer to the document for details about the design.

Prepare the design template in the Quartus Prime software GUI

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.

Development Kit

Intel® Arria® 10 SX SoC Development Kits

Design Details

Device Family

Intel® Arria® 10 SX 660 FPGA 10AS066N3F40E2SG
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

23.2