AN 824: Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

Download PDF
ID 683312
Date 8/08/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide x
OpenCL BSP Compilation Flow OpenCL BSP Floorplan Partition Guidelines for OpenCL BSP Floorplanning Guidelines for Maximum Operating Frequency Guidelines for Evaluating BSP Resource Utilization Efficiency Document Revision History
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

OpenCL BSP Compilation Flow

OpenCL BSP supports the following types of compile flows:
  • Flat compile [--bsp-flow flat]: Performs a flat compilation of the entire design (BSP along with kernel generated hardware).
  • Base compile [--bsp-flow base]: Performs a base compilation by using LogicLock restrictions from base.qsf file. The kernel clock target is relaxed so that the BSP hardware has more freedom to meet timing. A base.qar database is created to preserve the BSP hardware, which is the static region.
  • Import compile [<default>]: Restores the timing closed static region from the base.qar database and compiles only the kernel generated hardware. It also increases the kernel clock target to obtain the best kernel maximum operating frequency (fmax).
Level Two Title