Intel® Quartus® Prime Pro Edition Help version 21.3

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  • Welcome to the Intel® Quartus® Prime Pro Edition Software Help
    • Intel® Quartus® Prime Pro Edition Highlights
    • New Features in this Release
    • Terminology
    • Using Help Effectively
      • Opening the Glossary
      • Opening the Messages List
      • Using the Search
    • Starting the Intel® Quartus® Prime Software (quartus.exe) From the Command Line
  • Intel® Quartus® Prime Command Menu Reference
    • File Menu
      • Open Dialog Box
      • New Project Wizard
        • Use Existing Project Settings Dialog Box (New Project Wizard)
          • Use settings from last opened project
      • Save Project Command (File Menu)
      • Export Dialog Box (All Editors)
      • Convert Programming Files Command (File Menu)
      • Programming File Generator Command (File Menu)
      • Page Setup Dialog Box
      • Print Dialog Box
    • Edit Menu
      • Go To Dialog Box (Edit Menu)(Text Editor)
      • Go To Dialog Box (In-System Memory Content Editor)
      • Go To Dialog Box (Memory Editor)
    • View Menu
    • Project Menu
    • Assignments Menu
    • Processing Menu
    • Tools Menu
    • Task Window
      • Tcl Scripts Dialog Box (Tasks Window)
      • Customize Flow Dialog Box (Tasks Window)
  • Intel® Quartus® Prime Projects
    • quartus2.ini File
    • Settings Dialog Box
      • General Page (Settings Dialog Box)
        • Revision Type
      • Files Page (Settings Dialog Box)
      • Libraries Page (Settings Dialog Box)
      • General Settings for IP
      • Operating Settings and Conditions Page (Settings Dialog Box)
        • Voltage Page (Settings Dialog Box)
        • Temperature Page (Settings Dialog Box)
      • Compilation Process Settings Page (Settings Dialog Box)
      • EDA Tool Settings Page (Settings Dialog Box)
        • Design Entry/Synthesis (Settings Dialog Box)
        • Simulation (Settings Dialog Box)
          • Format for output netlist
          • Output Directory
          • Use Partial Line Selection
          • More EDA Netlist Writer Settings Dialog Box
            • Enable SDO Generation for Power Analysis
        • Board-level signal integrity analysis
      • Compiler Settings Page (Settings Dialog Box)
        • Advanced Synthesis Settings Dialog Box
        • Advanced Fitter Settings Dialog Box
        • VHDL Input Page (Settings Dialog Box)
        • Verilog HDL Input Page (Settings Dialog Box)
        • Default Parameters Page (Settings Dialog Box)
      • Design Assistant Rule Settings Dialog Box
      • Timing Analyzer Page (Settings Dialog Box)
        • SDC files to include in the project
        • Report worst-case paths during compilation
        • Tcl Script File for customizing reports during compilation
        • Metastability Analysis
      • Assembler Page (Settings Dialog Box)
      • Signal Tap Logic Analyzer Page (Settings Dialog Box)
      • Logic Analyzer Interface Page (Settings Dialog Box)
      • Power Analyzer Settings Page (Settings Dialog Box)
    • Options Dialog Box
      • General Page (Options Dialog Box)
      • Fonts Page (Options Dialog Box) (All Editors)
      • Headers & Footers Settings (Options Dialog Box)
      • Internet Connectivity Page (Options Dialog Box)
      • Block/Symbol Editor Page (Options Dialog Box)
      • Libraries Page (Options Dialog Box)
      • Design Templates (Options Dialog Box)
      • License Setup Page (Options Dialog Box)
      • Preferred Text Editor (Options Dialog Box)
      • General Settings for IP
      • Processing Page (Options Dialog Box)
      • Tooltip Settings Page (Options Dialog Box)
      • Messages Page (Options Dialog Box)
      • Memory Editor Page (Options Dialog Box)
      • Colors Page (Options Dialog Box) (All Editors)
      • Resource Property Editor Page (Options Dialog Box)
      • Text Editor Page (Options Dialog Box)
    • Project Navigator Window
      • Hierarchy tab
      • Files tab
      • Design Units tab
        • Design Unit Properties Dialog Box (Shortcut Menu)
      • IP Components Tab
        • Edit in Parameter Editor Command (Shortcut Menu)
      • Open in Main Window Command (Shortcut Menu)
    • Managing Project Revisions
      • Revisions Dialog Box
      • Create Revision Dialog Box
    • Archiving Projects
      • Advanced Archive Settings Dialog Box
      • Archive Project Dialog Box
    • Exporting Compilation Results
      • Export Design Dialog Box
      • Import Design Dialog Box
      • Partition Database File Viewer
  • Creating Design Files
    • Schematic/Block Editor
      • Edit Menu (Schematic/Block Editor)
        • Flip Commands (Edit Menu)
        • Line Commands (Edit Menu)
        • Rotate Commands (Edit Menu)
      • File Menu (Schematic/Block Editor)
      • Block Symbol File (New Dialog Box)
      • Block Diagram/Schematic File (New Dialog Box)
      • Show Commands (View Menu)
      • AutoFit Command
      • Arc Properties Dialog Box
      • Block Properties Dialog Box (Shortcut Menu)
      • Bus Properties Dialog Box
      • Circle Properties Dialog Box
      • Conduit Properties Dialog Box
      • Constant Properties Dialog Box
      • Create Design File from Selected Block Dialog Box
      • Create HDL Design File for Current File Dialog Box
      • Edit Selected Symbol Command (Shortcut Menu)
      • Generate Pins for Symbol Ports Command
      • Insert Symbol and Insert Symbol as Block Dialog Boxes
      • Line Properties Dialog Box
      • Mapper Properties Dialog Box
      • Multipage Setup Dialog Box
      • Node Properties Dialog Box (Block Editor)
      • Open Design File Command (Shortcut Menu)
      • Properties Dialog Box (Block & Symbol Editors)
      • Parameter Properties Dialog Box
      • Pin Properties Dialog Box
      • Port Properties Dialog Box
      • Rectangle Properties Dialog Box
      • Format Tab (Properties Command)
    • Text Editor
      • Autocomplete Text Command (Edit Menu)
      • Clear All Bookmarks (Current) Command (Edit Menu)
      • Clear All Bookmarks (All Files) Command (Edit Menu)
      • Comment Selection Command (Shortcut Menu)
      • Decrease Indent Command (Edit Menu)
      • Duplicate View Command (Shortcut Menu)
      • Find Matching Delimiter Command (Edit Menu)
      • Go To Dialog Box (Edit Menu)(Text Editor)
      • Increase Indent Command (Edit Menu)
      • Show Indentation Guide Command (View Menu)
      • Insert Constraint Command (Shortcut Menu)
      • Insert File Command (Edit Menu)
      • Insert Template Dialog Box
      • Jump To Next Bookmark Command (Edit Menu)
      • Jump To Previous Bookmark Command (Edit Menu)
      • Show Line Numbers Command (View Menu)
      • Word Wrap Command (View Menu)
      • Open AHDL Include File Command (Shortcut Menu)
      • Open Symbol File Command (Shortcut Menu)
      • Preferred Text Editor (Options Dialog Box)
      • Replace Tabs With Spaces Command (Edit Menu)
      • Show White Space Command (View Menu)
      • Split Window Command (Shortcut Menu)
      • Toggle Bookmark Command (Edit Menu)
      • Uncomment Selection Command (Shortcut Menu)
      • Save User Template Dialog Box
      • User Template Directory Dialog Box
      • Font Tab (Properties Command)
    • HDL Language Support
    • Memory Editor
      • New Memory Initialization File Command (Intel® Quartus® Prime Menu)
      • Insert Cells Command (Edit Menu)
      • Paste Insert Command (Edit Menu)
      • Reverse Address Contents Command (Edit Menu)
      • Fill Commands (Edit Menu) (Memory Editor)
      • Address Radix Commands (View Menu)
      • Cells Per Row Commands (View Menu)
      • Memory Radix Commands (View Menu)
      • Show ASCII Equivalents Command (View Menu)
      • Show Delimiter Spaces Command (View Menu)
      • Update Current Memory with Simulation Data Command (Processing Menu)
      • Update Memory Initialization File Command (Processing Menu)
      • Custom Fill Cells Dialog Box
      • Go To Dialog Box (Memory Editor)
      • Open Memory Dialog Box
      • Memory Size Wizard: Change Number of Word and Word Size Dialog Box
      • Number of Words & Word Size Dialog Box
  • Primitives
    • Alphabetical List of Primitives
      • OR Primitive
      • PARAM Primitive
      • Primitive/Port Interconnections
      • SOFT Primitive
      • SRFF Primitive
      • SRFFE Primitive
      • TFF Primitive
      • TFFE Primitive
      • Title Block Primitive
      • TRI Primitive
      • Unused Inputs to Primitives, Megafunctions & Macrofunctions
      • VCC (Block Design Files only) Primitive
      • WIRE (Block Design Files only) Primitive
      • XNOR Primitive
      • XOR Primitive
      • Pinstub Names in Primitives
      • WYSIWYG Atom Names Unavailable for Use as Primitive Instance Names
  • IP Cores
    • IP Catalog and Parameter Editor
    • Intel FPGA IP Cores/LPM
    • Clear Box Command-Line Tool
  • Timing Analysis
    • Timing Analyzer GUI
      • File Menu
      • View Menu
      • Netlist Menu
      • Constraints Menu
      • Reports Menu
      • Script Menu
      • Tools Menu
      • View Pane
      • Report Pane
      • Tasks Pane
      • Console
    • ::quartus::sdc
      • all_clocks (::quartus::sdc)
      • all_inputs (::quartus::sdc)
      • all_outputs (::quartus::sdc)
      • all_registers (::quartus::sdc)
      • derive_clocks (::quartus::sdc)
      • get_cells (::quartus::sdc)
      • get_clocks (::quartus::sdc)
      • get_nets (::quartus::sdc)
      • get_pins (::quartus::sdc)
      • get_ports (::quartus::sdc)
      • remove_clock_groups (::quartus::sdc)
      • remove_clock_latency (::quartus::sdc)
      • remove_clock_uncertainty (::quartus::sdc)
      • remove_disable_timing (::quartus::sdc)
      • remove_input_delay (::quartus::sdc)
      • remove_output_delay (::quartus::sdc)
      • reset_design (::quartus::sdc)
      • set_input_transition (::quartus::sdc)
      • set_disable_timing (::quartus::sdc)
    • ::quartus::sdc_ext
      • get_active_clocks (::quartus::sdc_ext)
      • get_assignment_groups (::quartus::sdc_ext)
      • get_fanins (::quartus::sdc_ext)
      • get_fanouts (::quartus::sdc_ext)
      • get_keepers (::quartus::sdc_ext)
      • get_nodes (::quartus::sdc_ext)
      • get_partitions (::quartus::sdc_ext)
      • get_registers (::quartus::sdc_ext)
      • remove_annotated_delay (::quartus::sdc_ext)
      • reset_timing_derate (::quartus::sdc_ext)
      • set_active_clocks (::quartus::sdc_ext)
      • set_annotated_delay (::quartus::sdc_ext)
      • set_max_skew (::quartus::sdc_ext)
      • set_net_delay (::quartus::sdc_ext)
      • set_scc_mode (::quartus::sdc_ext)
      • set_time_format (::quartus::sdc_ext)
      • set_timing_derate (::quartus::sdc_ext)
    • ::quartus::sta
      • add_to_collection (::quartus::sta)
      • check_timing (::quartus::sta)
      • create_report_histogram (::quartus::sta)
      • create_slack_histogram (::quartus::sta)
      • create_timing_netlist (::quartus::sta)
      • create_timing_summary (::quartus::sta)
      • delete_timing_netlist (::quartus::sta)
      • delete_sta_collection (::quartus::sta)
      • enable_ccpp_removal (::quartus::sta)
      • enable_sdc_extension_collections (::quartus::sta)
      • get_available_operating_conditions (::quartus::sta)
      • get_cell_info (::quartus::sta)
      • get_clock_domain_info (::quartus::sta)
      • get_clock_fmax_info (::quartus::sta)
      • get_clock_info (::quartus::sta)
      • get_datasheet (::quartus::sta)
      • get_default_sdc_file_names (::quartus::sta)
      • get_edge_info (::quartus::sta)
      • get_edge_slacks (::quartus::sta)
      • get_entity_instances (::quartus::sta)
      • get_min_pulse_width (::quartus::sta)
      • get_net_info (::quartus::sta)
      • get_node_info (::quartus::sta)
      • get_object_info (::quartus::sta)
      • get_operating_conditions (::quartus::sta)
      • get_operating_conditions_info (::quartus::sta)
      • get_partition_info (::quartus::sta)
      • get_path (::quartus::sta)
      • get_path_info (::quartus::sta)
      • get_pin_info (::quartus::sta)
      • get_point_info (::quartus::sta)
      • get_port_info (::quartus::sta)
      • get_register_info (::quartus::sta)
      • get_timing_paths (::quartus::sta)
      • locate (::quartus::sta)
      • query_collection (::quartus::sta)
      • read_sdc (::quartus::sta)
      • register_delete_timing_netlist_callback (::quartus::sta)
      • remove_from_collection (::quartus::sta)
      • report_advanced_io_timing (::quartus::sta)
      • report_bottleneck (::quartus::sta)
      • report_clock_fmax_summary (::quartus::sta)
      • report_clock_transfers (::quartus::sta)
      • report_clocks (::quartus::sta)
      • report_datasheet (::quartus::sta)
      • report_ddr (::quartus::sta)
      • report_max_skew (::quartus::sta)
      • report_metastability (::quartus::sta)
      • report_min_pulse_width (::quartus::sta)
      • report_ini_usage (::quartus::sta)
      • report_net_delay (::quartus::sta)
      • report_net_timing (::quartus::sta)
      • report_partitions (::quartus::sta)
      • report_path (::quartus::sta)
      • report_rskm (::quartus::sta)
      • report_sdc (::quartus::sta)
      • report_skew (::quartus::sta)
      • report_timing (::quartus::sta)
      • report_timing_tree (::quartus::sta)
      • report_tccs (::quartus::sta)
      • report_ucp (::quartus::sta)
      • set_operating_conditions (::quartus::sta)
      • timing_netlist_exist (::quartus::sta)
      • update_timing_netlist (::quartus::sta)
      • use_timequest_style_escaping (::quartus::sta)
      • write_sdc (::quartus::sta)
  • Integrating Other EDA Tools
    • EDA Tool Settings Page (Settings Dialog Box)
      • Design Entry/Synthesis (Settings Dialog Box)
      • Simulation (Settings Dialog Box)
        • Format for output netlist
        • Output Directory
        • Use Partial Line Selection
        • More EDA Netlist Writer Settings Dialog Box
          • Enable SDO Generation for Power Analysis
      • Board-level signal integrity analysis
    • Creating and Instantiating Intel® Quartus® Prime IP Cores in Other EDA Tools
    • Generating a Test Bench Template for Use with Other EDA Tools
      • Test Benches Dialog Box
    • Design Entry/Synthesis Tools
      • Precision RTL Synthesis Software
        • Setting Up the Precision RTL Synthesis Working Environment
        • Creating a Design for Use with the Precision RTL Synthesis Software
        • Setting Up a Project with the Precision RTL Synthesis Software
        • Assigning Design Constraints with the Precision RTL Synthesis Software
        • Generating EDIF Netlist Files with the Precision RTL Synthesis Software
      • Synplify Software
        • Synopsys® -Provided Logic Libraries
        • Setting Up the Synplify Working Environment
        • Creating a Design for Use with the Synplify Software
      • Setting Up the DK Design Suite Working Environment
    • Design Simulation
      • Simulator Support
      • Simulation Flows
      • Intel® Quartus® Prime Simulation Models
      • Compiling Intel FPGA simulation model files
      • Running EDA Simulators
        • Active-HDL
        • Questa® - Intel® FPGA Edition
          • Setting Up a Questa® - Intel® FPGA Edition Project
          • Performing a Gate-Level Functional Simulation with the Questa® - Intel® FPGA Edition Software
        • ModelSim® PE/SE/DE
          • Setting Up a Project with the ModelSim® Software
          • Performing a Gate-Level Functional Simulation with the ModelSim® Software
        • Xcelium™
          • Performing a Gate-Level Functional Simulation with the Cadence Xcelium™ Parallel Simulator Software
            • To perform a simulation of a Verilog HDL design with command-line commands using the Xcelium™ simulator
            • To perform a simulation of a VHDL design with command-line commands using the Xcelium™ simulator
        • QuestaSim
          • Setting Up a Project with the QuestaSim Software
          • Compiling Libraries and Design Files with the QuestaSim Software
          • Performing a Gate-Level Functional Simulation with the QuestaSim Software
        • Riviera Pro
        • VCS
        • VCS MX
          • Performing a Functional Simulation with the VCS MX Software
    • Generating Output Files for Board-Level Tools
      • Generating Board-Level Signal Integrity Analysis Files
        • Generating an IBIS Output File
          • Generating an IBIS Output File that contains only reserved pins and configuration pins
  • Platform Designer
    • Platform Designer File Menu
      • New BSP Command (File Menu) (Platform Designer)
      • Open BSP Command (File Menu) (Platform Designer)
      • Export BSP as Tcl Command (File Menu) (Platform Designer)
      • BSP Editor (Platform Designer)
    • Platform Designer Edit Menu
    • Platform Designer System Menu
    • Platform Designer Generate Menu
    • Platform Designer View Menu
      • HDL Parameters Tab (View Menu) (Platform Designer)
      • System Diff Tool Command (View Menu) (Platform Designer)
      • Preserve for Debug Command (Context Menu) (Platform Designer)
    • Platform Designer Tools Menu
    • Address Map Tab (Platform Designer)
    • Platform Designer Component Editor
      • Interfaces Tab (Platform Designer Component Editor)
      • Parameters Tab (Platform Designer Component Editor)
      • Template Command (Platform Designer Component Editor)
      • Add Commands (Templates Menu) (Component Editor)
      • Create Synthesis File From Signals Dialog Box (Component Editor) (Platform Designer)
    • Component Instantiation Tab (Platform Designer)
    • Element Docs Tab (Platform Designer)
    • Generation Dialog Box (Platform Designer)
    • Interface Requirements Tab
    • Presets Tab (Platform Designer)
      • New Preset Dialog Box (Platform Designer)
      • Update Preset Dialog Box (Platform Designer)
  • Design Constraints
    • Assignment Editor (Assignments Menu)
      • Location Dialog Box
      • Customize Columns Dialog Box
    • Pin Planner Command (Assignments Menu)
      • Pin Planner Options Page
      • Create Top-Level Design File Dialog Box
      • Assign Up, Down, Right, Left, and One by One Commands (Edit Menu)
        • Early Pin Planning Dialog Box
      • Pin Legend Window (View Menu)
      • Set Up Top-Level Design File Window (Edit Menu)
      • Show Commands (View Menu/Task Window) (Pin Planner)
      • Groups List Command (View Menu)
        • Edit Intel® FPGA IP (Shortcut Menu)
      • All Pins List Command (View Menu)
        • Customize Filter Dialog Box
        • New Filter Dialog Box
      • Pad View Window (View Menu)
      • Board Trace Model Window (View Menu)
      • Pin Migration View Window (View Menu)
        • Show Commands (Shortcut Menu) (Pin Migration View Window)
      • Resources Window (View Menu)
      • Task and Report Windows (Pin Planner)
      • Find Swappable Pins Dialog Box
      • Pin Finder Dialog Box
      • Group Dialog Boxes
      • Reserve Commands (Shortcut Menu)
      • Show Assignable Pins (Shortcut Menu)
      • Properties Dialog Boxes
    • Remove Assignments Dialog Box (Assignments Menu)
    • Back-Annotate Assignments Dialog Box
      • Node Filter Dialog Box
    • Import Assignments Dialog Box (Assignments Menu)
      • Assignment Categories Dialog Box
      • Advanced Import Settings Dialog Box
    • Interface Planner
      • Interface Planner Flow Control
      • Interface Planner Assignments Tab
      • Interface Planner Home Tab
      • Plan Tab
      • Interface Planner Reports Tab
  • Compilation Reports
    • Managing Reports
      • Compilation Report Command (Processing Menu)
      • Print Command (Report Window)
      • Navigating the Report Window
        • Expanding or Collapsing a Folder in the Report Window Contents
        • Opening Multiple Report Windows
        • Aligning Text in a Report Window Column
        • Copying text, charts, table cells, hierarchy entity names and speed performance table rows in reports:
        • Reordering and Hiding Columns in the Report Window
        • Saving a report window messages or logical memories section:
        • Printing the results of a compilation or simulation report:
      • Selecting reports to print
      • Include Report Section in Print List Command
      • Save Current Report Section As Command
      • Saving a report table
    • Synthesis Reports
      • Synthesis Summary Reports
      • Synthesis Settings Reports
      • Parallel Compilation Report
      • Synthesis Source Files Read Report
      • Source Assignments Report
      • Parameter Settings by Entity Instance Report
      • Synthesis Optimization Results Reports
      • Synthesis Partition Reports
      • Synthesis Connectivity Checks Report
      • Synthesis Resources Reports
      • State Machines Report
      • Equations Report
        • Note (1)
    • Fitter Reports
      • Plan Stage Reports
      • Place Stage Reports
        • Global Signal Visualization Report
      • Route Stage Reports
        • Global Router Wire Utilization Map Report
      • Retime Stage Reports
      • Finalize Stage Reports
      • Fitter Resources Reports
      • Clock Fmax Summary Report
      • Fitter I/O Rules Reports
    • Design Assistant Reports
    • Debug Tools Settings Summary Reports
      • Signal Tap Logic Analyzer Settings Report:
      • Signal Tap Logic Analyzer Instances Instantiated in Design Settings Report
      • In-System Memory Content Editor Settings Report
      • Logic Analyzer Interface Settings Report
      • Virtual JTAG Settings Report:
    • Timing Analyzer Multicorner Timing and Timing Model Datasheet Reports
    • Power Analyzer Reports
      • Power Analyzer Summary Report
      • Power Analyzer Settings Report
      • Power Analyzer Indeterminate Toggle Rates Report
      • Power Analyzer Generated Files Report
      • Power Analyzer Simulation Files Read Report
      • Power Analyzer Operating Conditions Report
      • Power Analyzer Thermal Power Dissipation by Block Report
      • Power Analyzer Thermal Power Dissipation by Block Type Report
      • Power Analyzer Thermal Power Dissipation by Hierarchy Report
      • Power Analyzer Core Dynamic Thermal Power Dissipation by Clock Domain
      • Power Analyzer Current Drawn from Voltage Supplies Summary Report
      • Power Analyzer VCCIO Supply Current Drawn by I/O Bank Report
      • Power Analyzer VCCIO Supply Current Drawn by Voltage Report
      • Power Analyzer VCCPD Supply Current Drawn by I/O Bank Report
      • Power Analyzer VCCPD Supply Current Drawn by Voltage Report
      • Power Analyzer Confidence Metric Report
      • Power Analyzer Signal Activities Report
      • Power Analyzer Messages Report
      • Early Power Estimator File Generator Reports
    • Assembler Reports
    • EDA Netlist Writer Reports
      • EDA Netlist Writer Summary Report:
      • EDA Netlist Writer Simulation Reports:
      • EDA Netlist Writer Formal Verification Tools Report
      • EDA Netlist Writer Board-Level Tools Reports
      • EDA Netlist Writer Messages
    • SEU FIT Report
    • Simulation Flow Reports
    • Legal Notice Section (Compilation or Simulation Report)
  • Viewing Messages
    • Messages Window
      • Getting Source Location Information about a Message
      • Viewing Messages in the Report Window
    • Message Suppression Manager Dialog Box
    • Messages Page (Options Dialog Box)
    • Clear Messages from Window Command (Shortcut Menu)
    • Clear All Flags Command (Shortcut Menu)
    • Clear Flag Command (Shortcut Menu)
    • Flag Message Command (Shortcut Menu)
    • Hide Previous Compilation Messages Command (Shortcut Menu)
    • Load Messages from the Compilation Report (Shortcut Menu)
    • Save Messages Command (Shortcut Menu)
    • Select Text Command (Shortcut Menu)
    • Show All Submessages Command (Shortcut Menu)
    • Clear Sorting Command (Shortcut Menu)
    • Suppress All Flagged Messages Command (Shortcut Menu)
    • Suppress Messages with Matching ID Command (Shortcut Menu)
    • Suppress Messages with Matching Keyword Command (Shortcut Menu)
    • Suppress Message Command (Shortcut Menu)
    • Export Message Flag Rule File Dialog Box
    • Export Message Suppression Rule File Dialog Box
    • Import Message Flag Rule File Dialog Box
    • Import Message Suppression Rule File Dialog Box
    • Suppress by Keyword Dialog Box
  • Advisors in the Intel® Quartus® Prime Software
    • Recommendations in Advisors
    • Intel® Arria® 10 to Intel® Stratix® 10 Migration Advisor Command (Tools Menu)
    • Compilation Time Advisor Command (Tools Menu)
    • Power Optimization Advisor Command (Tools Menu)
    • Timing Optimization Advisor Command (Tools Menu)
  • Compilation
    • Compilation Dashboard
    • Snapshot Viewer Commands
    • Compilation Commands
    • Compiler Settings
      • Device Page (Settings Dialog Box)
        • Device and Pin Options Dialog Box
          • General Page (Device and Pin Options Dialog Box)
            • Delay Entry to User Mode
            • Configuration Clock Source
          • Configuration Page (Device and Pin Options Dialog Box)
          • Programming Files Page (Device and Pin Options Dialog Box)
          • Unused Pins Page (Device and Pin Options Dialog Box)
          • Dual-Purpose Pins Page (Device and Pin Options Dialog Box)
          • Board Trace Model Page (Device and Pin Options Dialog Box)
          • I/O Timing Page (Device and Pin Options Dialog Box)
          • Voltage Page (Device and Pin Options Dialog Box)
          • Error Detection CRC Page (Device and Pin Options Dialog Box)
            • Enable error detection check
            • Minimum SEU interval
          • CvP Settings Page (Device and Pin Options Dialog Box)
          • Partial Reconfiguration Page (Device and Pin Options Dialog Box)
          • Power Management & VID Page (Device and Pin Options Dialog Box)
          • Security Page (Device and Pin Options Dialog Box)
          • More Security Options Dialog Box
        • Board Page (Settings Dialog Box)
      • Allow Register Retiming
      • Fast Preserve Option
      • Migration Devices Dialog Box
      • Recommendations Dialog Box
    • Place and Route
      • Start Fitter Commands (Processing Menu)
  • Partial Reconfiguration
    • Design Partitions Window
    • Set As Design Partition Command (Shortcut Menu)
    • Export Design Partition Dialog Box
  • Generating Programming Files
    • Convert Programming Files Dialog Box
      • Add Hex Data
      • Convert Programming Files - Advanced Options Dialog Box
      • Hexadecimal File Options Dialog Box
      • SOF Data Properties Dialog Box
      • SOF File Properties Dialog Box
      • PMSF File Properties Dialog Box
    • Assembler Page (Settings Dialog Box)
    • Programming File Generator
      • Output Files Tab
      • Input Files Tab
      • Input File Properties Dialog Box
      • Configuration Device Tab
      • Edit Partition Dialog Box
      • Add Partition Dialog Box (Programming File Generator)
    • OpenCore Plus Status Dialog Box
  • Programming Devices
    • Programmer Options Dialog Box
    • Programmer
      • Properties Dialog Box (Programmer)
      • Auto Detect Command (Processing Menu)
      • Show Device Tree/Pane (View Menu)
      • Define CFI Flash Device Command (Edit Menu)
      • ISP CLAMP State Editor Window (Edit Menu)
      • Delete POF Command (Edit Menu)
      • Delete IPS File Command (Edit Menu) (Programmer)
      • Flash Device Commands (Edit Menu)
      • Hardware Setup Dialog Box
      • Save Data To File As Dialog Box
      • Create JAM, JBC, SVF, or ISC File Dialog Box
      • Select New I/O Pin State File Dialog Box
      • Select New Programming File Dialog Box
      • Select New Device Dialog Box
        • Export User-Defined Device Dialog Box
      • Select I/O Pin State File Dialog Box
      • Select Programming File Dialog Box
      • Select Devices Dialog Box
      • Device's Properties Dialog Box
      • Select Flash Device Dialog Box
      • Select New Flash Device Dialog Box
      • Select Device Dialog Box
        • Import User Devices Dialog Box
        • Edit Device Dialog Box
        • New Device Dialog Box
          • Add JTAG ID Dialog Box
      • New CFI Flash Device Dialog Box
      • Select POF Dialog Box
    • Open JTAG Chain Log File Dialog Box
    • JTAG Chain Debugger
  • Debugging your Design
    • System Console
      • File Menu
        • Execute Script Dialog Box
        • Refresh Connections
        • Load Design
      • Tools Menu
        • Autosweep View
        • Dashboard View
        • Eye Viewer
      • View Menu
      • Help Menu
        • System Console Documentation Command
        • About System Console Window
    • In-System Memory Content Editor
      • JTAG Chain Configuration Pane (In-System Memory Content Editor)
      • Instance Manager Pane (ISMCE)
      • Export Data to File Dialog Box
      • Go To Dialog Box (In-System Memory Content Editor)
      • Import Data from File Dialog Box
      • Read Information from In-System Memory Commands (Processing Menu)
      • Stop In-System Memory Analysis Command (Processing Menu)
      • Write Information to In-System Memory Commands (Processing Menu)
      • Select Range Dialog Box
      • Custom Fill Dialog Box
    • Signal Tap Logic Analyzer
      • Signal Tap Logic Analyzer Options Dialog Box
      • View Page (Signal Tap Logic Analyzer) (Options Dialog Box)
        • Signal Tap Logic Analyzer Page (Settings Dialog Box)
      • File Menu
        • Create Signal Tap List File Command (File Menu)
          • Create Signal Tap File from Design Instance(s) Command (File Menu)
        • Print Options Dialog Box (Signal Tap Logic Analyzer)
        • Create Simulation Testbench Dialog Box (Signal Tap Logic Analyzer)
      • Edit Menu
        • Find Bus Value Dialog Box
        • Plug-In Options Dialog Box
        • Simulator-Aware Node Finder Dialog Box
        • Create/Delete/Rename Instance Commands (Edit Menu)
        • Enable/Disable Power-up Trigger/Duplicate Trigger Commands (Edit Menu)
        • Bus Bit Order Commands (Edit Menu)
        • Bus Display Format Commands (Edit Menu)
        • Mnemonic Table Setup Dialog Box
          • Add Table Dialog Box
          • Add Entry Dialog Box
          • Import Table Dialog Box
        • Recreate State Machine Mnemonics Command (Edit Menu)
          • Recreate State Machine Mnemonics Dialog Box
        • Save to Data Log/Enable Data Log Commands (Edit Menu)
        • Use As Commands (Edit Menu)
        • Add State Machine Nodes Dialog Box
      • View Menu
        • Fit in Window/Zoom In/Zoom Out/Center on Trigger Commands (View Menu)
        • Instance Manager Pane (View Menu) (Signal Tap Logic Analyzer)
        • JTAG Chain Configuration Pane (Signal Tap Logic Analyzer)
        • Signal Configuration Pane (View Menu) (Signal Tap Logic Analyzer)
        • Hierarchy Display Pane (View Menu) (Signal Tap Logic Analyzer)
        • Data Log Pane (View Menu) (Signal Tap Logic Analyzer)
        • Delete All Time Bars/Next Transition/Previous Transition Commands (View Menu)
        • Insert Time Bar Dialog Box
        • Sample Numbers Command (View Menu)
        • Time Units Dialog Box
        • Delete All Time Bars/Next Transition/Previous Transition Commands (View Menu)
      • Analysis Commands (Processing Menu)
      • Setup Tab (Signal Tap Logic Analyzer)
        • Node List Pane (Signal Tap Logic Analyzer)
        • Insert Value Dialog Box
      • State-Based Trigger Flow Tab (Signal Tap Logic Analyzer)
      • Advanced Trigger Tab (Signal Tap Logic Analyzer)
        • Example of Using a Bitwise Object in an Advanced Trigger Condition
        • Examples of Constructing Advanced Trigger Conditions for the Signal Tap Logic Analyzer
        • Example of Using Data Delay in an Advanced Trigger Condition
        • Example of Using a Comparison Object and Pipelining in an Advanced Trigger Condition
        • Example of Using an Edge & Level Detector Object and Logical Conditions in an Advanced Trigger Condition
        • Example of Using a Shift Object in an Advanced Trigger Condition
        • Object Library Pane (Signal Tap Logic Analyzer)
      • Data Tab (Signal Tap Logic Analyzer)
        • Waveform Display Pane (Signal Tap Logic Analyzer)
          • Invert Signal Command (Shortcut Menu)
        • Master Time Bar Commands (Shortcut Menu)
      • SOF Manager Commands
      • Rename Command (Shortcut Menu) (Signal Tap Logic Analyzer)
      • State Diagram Pane (Signal Tap Logic Analyzer)
      • State Machine Pane (Signal Tap Logic Analyzer)
      • Resources Pane (Signal Tap Logic Analyzer)
      • Find Bus Value Commands
    • Logic Analyzer Interface
      • Logic Analyzer Interface Editor (Tools Menu)
    • In-System Sources and Probes
      • Instance Manager Pane (In-System Sources and Probes Editor)
      • Select JTAG Debugging Information File Dialog Box
      • Set Alias/Delete Alias Commands (Edit Menu)
      • Bus Bit Order Commands (Edit Menu)
      • Bus Display Format Commands (Edit Menu)
      • Recreate Instances Commands (Edit Menu)
      • Set Value of Source Commands (Edit Menu)
      • JTAG Chain Configuration Pane (In-System Sources and Probes Editor)
      • Read Probe Data Commands (Processing Menu)
      • Source Data Commands (Processing Menu)
  • Design Space Explorer II Tool
    • Status Page (Design Space Explorer II)
  • Design Partition Planner Tool
    • Design Partition Planner Commands
    • Bundle Configuration Dialog Box (Design Partition Planner)
    • Bundle Properties Dialog Box (Design Partition Planner)
    • Options Dialog Box (Design Partition Planner)
    • Design Partition Planner Interface
  • Power Estimation and Analysis
    • Power Analyzer Tool
    • Add/Edit Power Input File Dialog Box
    • Generate Early Power Estimator File Command (Project Menu)
    • HPS Power Calulator Dialog Box
    • Select Hierarchy Dialog Box
    • Power Analyzer Assignment Names
  • Chip Planner
    • Chip Planner Options Dialog Box
    • View Menu (Chip Planner)
      • Locate Node Commands
      • Task Window Command (View Menu)
    • Edit Menu (Chip Planner)
    • Resource Property Editor Page (Options Dialog Box)
    • Tasks Pane (Chip Planner)
      • Partition Reports
      • Selection Reports
    • Report Window (Chip Planner)
      • Properties dialog box (Report Window) (Chip Planner)
      • Report Resources Dialog Box (Chip Planner)
      • Report Compilation Messages Dialog Box (Chip Planner)
      • Report Registered Connections Dialog Box (Chip Planner)
      • Report Used Clock Regions Dialog Box (Chip Planner)
      • Report Spine Clock Utilization dialog box (Chip Planner)
      • Report HSSI Block Connectivity dialog box (Chip Planner)
      • Report Design Partitions Advanced Dialog Box (Chip Planner)
      • Report Selection Contents
    • Locate History Pane (Chip Planner)
    • Properties Tab (Chip Planner)
    • Layers Settings Pane
    • Bird's Eye View Window
    • Schematic View (Chip Planner)
  • Logic Lock Regions
    • Logic Lock Regions Window
    • Logic Lock Region Properties Dialog Box
      • Shapes tab
    • Region Filter Dialog Box
    • Rename Region Dialog Box
    • Logic Lock Region Assignments
  • Using the Netlist Viewer
    • Bird's Eye View Command (View Menu)
    • Hide Selection Commands (Shortcut Menu)
    • Filter Commands (Shortcut Menu)
    • Expand to Upper Hierarchy (Shortcut Menu)
    • Generate HDL File Command (Tools Menu)
    • Input Ports List/Ouput Ports List Commands (View Menu)
    • Properties Pane (Netlist Viewers)
    • RTL Viewer Command (Tools Menu)
    • Generate Other Files Dialog Box
    • Technology Map Viewer Command (Tools Menu)
    • Select Bus Index Dialog Box
    • Find Options Dialog Box (Netlist Viewers)
    • Find Pane (Netlist Viewers)
  • Verifying with the Design Assistant
    • Design Assistant Rule Settings Dialog Box
    • Filter Options Dialog Box
    • Design Assistant Rules List
      • New and Updated Design Assistant Rules for 21.3 Release
        • CDC-50001: 1-Bit Asynchronous Transfer Not Synchronized
        • CDC-50002: 1-Bit Asynchronous Transfer with Insufficient Constraints
        • CDC-50003: CE-Type CDC Transfer with Insufficient Constraints
        • CDC-50004: MUX-type CDC Transfer with Insufficient Constraints
        • CDC-50005: CDC Bus Constructed with Multi-bit Synchronizer Chains of Different Lengths
        • CDC-50006: CDC Bus Constructed with Unsynchronized Registers
        • CDC-50007: CDC Bus Constructed with Multi-bit Synchronizer Chains with Insufficient Constraints
        • CDC-50008: CDC Bus Constructed with Multi-bit Synchronizer Chains
        • CDC-50011: Combinational Logic Before Synchronizer Chain
        • CDC-50012: Multiple Clock Domains Driving a Synchronizer Chain
        • CDC-50101: Intra-Clock False Path Synchronizer
        • CDC-50102: Synchronizer after CDC Topology with Control Signal
        • CDC-50103: Unsynchronized Intra-Clock Forced Synchronizer
        • CLK-30001: Gated Clock Should Feed a Predefined Number of Clock Ports for Power Efficiency
        • CLK-30002: Clock Source Driving Non-clock Pins
        • CLK-30026: Missing Clock Assignment
        • CLK-30027: Multiple Clock Assignments Found
        • CLK-30028: Invalid Generated Clock
        • CLK-30029: Invalid Clock Assignments
        • CLK-30030: PLL Setting Violation
        • CLK-30031: Input Delay Assigned to Clock
        • CLK-30032: Improper Clock Targets
        • CLK-30033: Invalid Clock Group Assignment
        • CLK-30034: Clock Pairs Missing Logically Exclusive Clock Group Assignment
        • CLK-30035: Clock Pairs Missing Physically Exclusive Clock Group Assignment
        • CLK-30042: Incorrect Clock Group Type
        • FLP-10000: Physical RAM with Utilization Below Threshold
        • FLP-10100: Large Multipliers are Decomposed
        • FLP-10500: Non Driving Top Level Inputs Found
        • FLP-40001: Congested Placement Region
        • FLP-40002: Very Small Routing Regions
        • FLP-40003: Narrow Region
        • FLP-40005: Congested Routing Region
        • FLP-40006: Pipelining Registers That Might Be Recoverable
        • LNT-30010: Nets Driving both Reset and Clock Enable Signals
        • LNT-30011: Design Contains Combinational Loops
        • LNT-30012: Design Contains Latches
        • LNT-30013: Design Contains Ripple Clock Structures
        • LNT-30014: Asynchronous Pulse Generators
        • LNT-30015: Multiple Pulses Generated in the Design
        • LNT-30016: Design Contains SR Latches
        • LNT-30017: Register Output Driving Its Own Control Signal Directly or Through Combinational Logic
        • LNT-30018: Design Contains Delay Chains
        • LNT-30020: Same Signal Source Drives Synchronous and Asynchronous Ports of the Same Register
        • LNT-30021: Same Signal Source Drives More Than One Asynchronous Port of a Register
        • LNT-30022: Same Signal Source Drives Clock Port and Another Port of a Register
        • LNT-30023: Reset Nets with Polarity Conflict
        • PRJ-10000: INI Variables Used During Compile
        • PRJ-10001: INI Variables Set and Not Used During Compile
        • RDC-50001: Reconvergence of Multiple Asynchronous Reset Synchronizers in Different Reset Domains
        • RDC-50002: Reconvergence of Multiple Asynchronous Reset Synchronizers in a Common Reset Domain
        • RES-10201: Power Up Don't Care Setting May Prevent Retiming
        • RES-10202: Register Power-Up Settings Conflict with Device Settings
        • RES-10203: Register Initial Condition Check
        • RES-10204: Reset Release Instance Count Check
        • RES-30132: Registers May Not Be Properly Reset
        • RES-30133: Embedded Memory Blocks with Initialized Content That Might be Affected by Spurious Writes
        • RES-30134: Registers Not Reachable from Reset Release IP
        • RES-50001: Asynchronous Reset Is Not Synchronized
        • RES-50002: Asynchronous Reset is Insufficiently Synchronized
        • RES-50003: Asynchronous Reset with Insufficient Constraints
        • RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain
        • RES-50005: RAM Control Signals Driven by Flip-Flops with Asynchronous Clears
        • RES-50010: Reset Synchronizer Chains with Constant Output
        • RES-50101: Intra-Clock False Path Reset Synchronizer
        • TMC-10107: Maximum Fan-out for Signal
        • TMC-10115: High Fan-out Signal
        • TMC-20001: Timing Paths with Hold Slack Exceeding Threshold
        • TMC-20002: Timing Paths with Removal Slack Exceeding Threshold
        • TMC-20004: Timing Paths with Setup Slack Exceeding Threshold
        • TMC-20005: Timing Paths with Recovery Slack Exceeding Threshold
        • TMC-20006: Unregistered Partition Inputs
        • TMC-20007: Unregistered Paths Between Partitions
        • TMC-20010: Logic Level Depth
        • TMC-20011: Missing Input Delay Constraint
        • TMC-20012: Missing Output Delay Constraint
        • TMC-20013: Partial Input Delay
        • TMC-20014: Partial Output Delay
        • TMC-20015: Inconsistent Min-Max Delay
        • TMC-20016: Invalid Reference Pin
        • TMC-20017: Loops Detected
        • TMC-20018: Latches Detected
        • TMC-20019: Partial Multicycle Assignment
        • TMC-20020: Invalid Multicycle Assignment
        • TMC-20021: Partial Min-Max Delay Assignment
        • TMC-20022: Incomplete I/O Delay Assignment
        • TMC-20023: Invalid Set Net Delay Assignment
        • TMC-20024: Synchronous Data Delay Assignment
        • TMC-20025: Ignored or Overridden Constraints
        • TMC-20026: Empty Collection Due To Unmatched Filter
        • TMC-20027: Collection Filter Matching Multiple Types
        • TMC-20050: RAM Control Signals Driven by LUTs or ALMs instead of DFFs
        • TMC-20051: RAM Control Signals Driven by High Fan-Out Net
        • TMC-20052: Paths with Post Synthesis Inferred Latches
        • TMC-20053: DSP Inputs Driven by High Fan-Out Net
        • TMC-20100: Latch Loops Detected
        • TMC-20200: Paths Failing Setup Analysis with Impossible Requirements
        • TMC-20201: Paths Failing Setup Analysis with High Clock Skew
        • TMC-20202: Paths Failing Setup Analysis with High Logic Delay
        • TMC-20203: Paths Failing Setup Analysis with High Fabric Interconnect Delay
        • TMC-20204: Endpoints of Paths Failing Setup Analysis with Retiming Restrictions
        • TMC-20205: Endpoints of Paths Failing Setup Analysis with Explicit Power-Up States that Restrict Retiming
        • TMC-20206: DSP Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
        • TMC-20207: DSP Blocks with Unregistered Inputs that are the Destination of Paths Failing Setup Analysis
        • TMC-20208: RAM Blocks with Unregistered Outputs that are the Source of Paths Failing Setup Analysis
        • TMC-20209: Paths Failing Setup Analysis with High Routing Delay due to Congestion
        • TMC-20210: Paths Failing Setup Analysis with High Routing Delay Added for Hold
        • TMC-20212: Paths Failing Setup Analysis with Global Routing in Data Path
        • TMC-20213: Paths Failing Setup Analysis with Locally Routed Clock
        • TMC-20214: Buses with Incoming Paths Failing Setup Analysis with Multiple Sequential Adder Chains
        • TMC-20215: Buses with Incoming Paths Failing Setup Analysis with Multipliers Implemented in Logic
        • TMC-20216: Paths Failing Setup Analysis with Inferred-RAM Shift Register Endpoints
        • TMC-20217: Paths Failing Setup Analysis with Clock-As-Data
        • TMC-20219: DSP Blocks with Restricted Fmax below Required Fmax
        • TMC-20220: RAM Blocks with Restricted Fmax below Required Fmax
        • TMC-20221: Nodes Failing Minimum Pulse Width Due to Clock Pulse Collapse
        • TMC-20250: Paths Failing Setup Analysis within Platform Designer Interconnect
        • TMC-20251: Paths Failing Setup Analysis within Platform Designer Interconnect Burst Adapter
        • TMC-20312: Paths Failing Hold Analysis with Global Routing in Data Path
        • TMC-20313: Paths Failing Hold Analysis with Locally Routed Clock
        • TMC-20500: Hierarchical Tree Duplication was Shallower than Possible
        • TMC-20501: Hierarchical Tree Duplication was Shallower than Requested
        • TMC-20550: Automatically Selected Duplication Candidate Rejected for Placement Constraint
        • TMC-20551: Automatically Selected Duplication Candidate Likely Requires More Duplication
        • TMC-20552: User Selected Duplication Candidate was Rejected
        • TMC-20601: Registers with High Immediate Fan-Out Tension
        • TMC-20602: Registers with High Timing Path Endpoint Tension
        • TMC-20603: Registers with High Immediate Fan-Out Span
        • TMC-20604: Registers with High Timing Path Endpoint Span
        • TMC-20605: Register Wirelut FO Check
        • TMC-20712: Paths Failing Recovery Analysis with Global Routing in Data Path
        • TMC-20713: Paths Failing Recovery Analysis with Locally Routed Clock
        • TMC-20812: Paths Failing Removal Analysis with Global Routing in Data Path
        • TMC-20813: Paths Failing Removal Analysis with Locally Routed Clock
        • TMC-30041: Constraint with Invalid Clock Reference
  • Devices and Adapters
    • Devices and Adapters
  • Logic Options
    • Logic Options by Category
      • Advanced logic options
      • Global Signals logic options
      • Synchronize selections between tools
      • I/O Timing logic options
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      • Fitter Optimization
      • Others
    • All Logic Options
  • Intel® Quartus® Prime Scripting Support
    • Generate Tcl File for Project Dialog Box
    • Tcl Scripts (Tools Menu)
    • Tcl Console Command (View menu)
    • Examples of Assignment Syntax and Formatting in the Intel® Quartus® Prime Settings File
    • Organize Intel® Quartus® Prime Settings File Command (Project Menu)
  • Keyboard Shortcuts and Toolbar Buttons
  • Glossary
    • file types Definition
    • Secure Mask Settings File (.smsf)
  • TCL Commands and Packages
  • List of Messages