TMC-20052: Paths with Post Synthesis Inferred Latches
Description
Design Assistant detected one or more inferred latches remaining after synthesis. Inferred latches are often unintended in FPGA designs.
Recommendation
Remove any unintended inferred latches from the design.
Severity
Medium
Tags
| Tag | Description |
|---|---|
| nonstandard-timing | Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic. |
| latch | Design rule checks related to latches. |
Device Family
- Intel®Agilex™
- Intel®Stratix® 10
- Intel®Arria® 10
- Intel®Cyclone® 10 GX