RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain
Description
Violations of this rule identify asynchronous reset synchronizer chains where not all of the registers are reset by the same signal. Such chains do not properly synchronize the reset signal feeding the head of the chain. This condition can cause metastablity in downstream data signals.
Recommendation
Ensure that there is a common source that feeds the asynchronous reset pin of every register in the same asynchronous reset synchronizer chain.
Severity
High
Tags
Tag | Description |
---|---|
synchronizer | Design rule checks related to synchronizer chains. |
Device Family
- Intel®Cyclone® 10 GX
- Intel®Arria® 10
- Intel®Stratix® 10
- Intel®Agilex™