Design Assistant Reports

Summarizes the following information about the compilation:

• Design Assistant Status shows the final status, end date, and end time of the Design Assistant process.
• Revision Name shows the revision name specified in the Revisions dialog box.
• Top-level Entity Name
• Family shows the device family name specified in the Device dialog box of the Settings dialog box.
• Total Critical Violations, Total High Violations, Total Medium Violations, and Total Information Only Violations, are violations of the rules, some of which might affect the reliability of the design.

Reports the settings for the Design Assistant you specified in the Design Assistant page of the Settings dialog box.

The Design Assistant mode option can have a value of pre-synthesis, post-fitting, or post-synthesis, depending on which point in the design flow you run the Design Assistant. The Threshold value for clock net not mapped to clock spines rule option shows the threshold for reporting nodes with a specified minimum number of fanouts. The Minimum number of node fan-out option shows the minimum fan-out the Design Assistant reports. The Maximum number of nodes to report option shows the maximum number of high fan-out nodes the Design Assistant reports. The remaining options are either turned on or off and are described on the Design Assistant Rules page.

Reports detailed information about the rule violations reported by the Design Assistant including the Rule name, the node Name, and the Fan-Out. This report only appears if you specify settings in the Design Assistant page of the Settings dialog box.

Separate Design Assistant Detailed Results reports are generated for critical, high, medium, and information-only results.

Reports any messages generated by the Design Assistant during the current process. The Design Assistant generates info, warning, and error messages that report on conditions observed during the Design Assistant process.

You can right-click a message in the Design Assistant Messages report and click Help to display help on the selected message, or click Locate to view a list of options available for the selected node(s).

Reports detailed information about which rules are enabled or disabled, as controlled by the suppression assignments that you can set in the Assignment Editor, Quartus Prime Standard Edition Settings File (.qsf) Definition, Verilog HDL Definition, or VHDL Definition. These assignments include the following:

• Assignment shows the name of the assignment.
• Value identifies the rule.
• To shows the node name to which the rule is being applied.
• Comment shows whether the suppression assignment is honored.

Reports detailed information about the invalid and conflicting rule assignments reported by the Design Assistant, including:

• Assignment shows the name of the assignment.
• Value identifies the rule.
• To shows the node name to which the rule is being applied.
• Comment shows why the assignment is being ignored.

This report only appears if you specify an invalid rule ID in the rule suppression or a conflicting rule assignment. You can make assignments in the Assignment Editor, Quartus Prime Standard Edition Settings File (.qsf) Definition, Verilog HDL Definition, or VHDL Definition.

Lists the source file for any custom rules used by your design.

Lists the Rule ID and source file for any custom rules used by your design.