Directs the Compiler or Simulator to process Verilog Design File (.v) Definition using the specified standard. You can select one of the following options:
Standard |
Description |
|---|---|
Verilog-1995 |
Directs the Compiler or Simulator to process Verilog HDL Design Files using the IEEE Std 1394-2001 Verilog HDL standard. |
Verilog-2001 |
Directs the Compiler or Simulator to process Verilog HDL Design Files using the IEEE Std 1364-2001 Verilog HDL standard. This is the default option. |
SystemVerilog-2005 |
Directs the Compiler or Simulator to process Verilog HDL Design Files using the IEEE Std 1800-2005 SystemVerilog standard. |
 Scripting
Information |
Keyword:verilog_input_version Settings:verilog_1995|verilog_2001|systemverilog_2005 *default |