You can use the EDA Netlist Writer module to generate VHDL Output File (.vho) DefinitionVerilog Output File (.vo) Definition and Standard Delay Format Output File (.sdo) Definition for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design.
You can also use this command to generate the following types of files:
You can also generate netlist files for use by third-party EDA tools with the IP Catalog.