ddr_scheduler_fpga2sdram_manager_main_SidebandManager Address Map
| Module Instance | Base Address | End Address |
|---|---|---|
| soc_ddr_scheduler_inst_0_fpga2sdram_manager_main_SidebandManager | 0xF8024000 | 0xF80240FF |
| Register | Offset | Width | Access | Reset Value | Description |
|---|---|---|---|---|---|
| fpga2sdram_manager_main_SidebandManager_Id_CoreId | 0x0 | 32 | RO | 0x9885CB0B |
FPGA2SDRAM Manager Sideband Manager Core ID Register |
| fpga2sdram_manager_main_SidebandManager_Id_RevisionId | 0x4 | 32 | RO | 0x00014800 |
FPGA2SDRAM Manager Sideband Manager Revision ID Register |
| fpga2sdram_manager_main_SidebandManager_FaultEn | 0x8 | 32 | RW | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Fault Enable ID Register |
| fpga2sdram_manager_main_SidebandManager_FaultStatus | 0xC | 32 | RO | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Fault Status Register |
| fpga2sdram_manager_main_SidebandManager_FlagInEn0 | 0x10 | 32 | RW | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Flag Interrupt Enable 0 Register |
| fpga2sdram_manager_main_SidebandManager_FlagInStatus0 | 0x14 | 32 | RO | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Flag Interrupt Status 0 Register |
| fpga2sdram_manager_main_SidebandManager_FlagOutSet0 | 0x50 | 32 | RW | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Flag Out Set 0 Register |
| fpga2sdram_manager_main_SidebandManager_FlagOutClr0 | 0x54 | 32 | RW | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Flag Out Clear 0 Register |
| fpga2sdram_manager_main_SidebandManager_FlagOutStatus0 | 0x58 | 32 | RO | 0x00000000 |
FPGA2SDRAM Manager Sideband Manager Flag Out Status 0 Register |