fpga2sdram_manager_main_SidebandManager_Id_CoreId
FPGA2SDRAM Manager Sideband Manager Core ID Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_ddr_scheduler_inst_0_fpga2sdram_manager_main_SidebandManager | 0xF8024000 | 0xF8024000 |
Size: 32
Offset: 0x0
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
CORECHECKSUM RO 0x9885CB |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CORECHECKSUM RO 0x9885CB |
CORETYPEID RO 0xB |
||||||||||||||
fpga2sdram_manager_main_SidebandManager_Id_CoreId Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 | CORECHECKSUM |
Field containing a checksum of the parameters of the IP. |
RO | 0x9885CB |
| 7:0 | CORETYPEID |
Field identifying the type of IP. |
RO | 0xB |