fpga2sdram_manager_main_SidebandManager_FlagInEn0

         FPGA2SDRAM Manager Sideband Manager Flag Interrupt Enable 0 Register

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_fpga2sdram_manager_main_SidebandManager`	`0xF8024000`	`0xF8024010`

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`FPGA2SDRAM2_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM2_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM2_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM2_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM1_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM0_IDLE_EN` `RW 0x0`

fpga2sdram_manager_main_SidebandManager_FlagInEn0 Fields

Bit	Name	Description	Access	Reset
11	`FPGA2SDRAM2_RESP_IDLE_EN`	FlagIn Enable register #11.FPGA2SDRAM2_RESP_IDLE_EN	`RW`	`0x0`
10	`FPGA2SDRAM2_CMD_IDLE_EN`	FlagIn Enable register #10.FPGA2SDRAM2_CMD_IDLE_EN	`RW`	`0x0`
9	`FPGA2SDRAM2_IDLEACK_EN`	FlagIn Enable register #9.FPGA2SDRAM2_IDLEACK_EN	`RW`	`0x0`
8	`FPGA2SDRAM2_IDLE_EN`	FlagIn Enable register #8.FPGA2SDRAM2_IDLE_EN	`RW`	`0x0`
7	`FPGA2SDRAM1_RESP_IDLE_EN`	FlagIn Enable register #7.FPGA2SDRAM1_RESP_IDLE_EN	`RW`	`0x0`
6	`FPGA2SDRAM1_CMD_IDLE_EN`	FlagIn Enable register #6.FPGA2SDRAM1_CMD_IDLE_EN	`RW`	`0x0`
5	`FPGA2SDRAM1_IDLEACK_EN`	FlagIn Enable register #5.FPGA2SDRAM1_IDLEACK_EN	`RW`	`0x0`
4	`FPGA2SDRAM1_IDLE_EN`	FlagIn Enable register #4.FPGA2SDRAM1_IDLE_EN	`RW`	`0x0`
3	`FPGA2SDRAM0_RESP_IDLE_EN`	FlagIn Enable register #3.FPGA2SDRAM0_RESP_IDLE_EN	`RW`	`0x0`
2	`FPGA2SDRAM0_CMD_IDLE_EN`	FlagIn Enable register #2.FPGA2SDRAM0_CMD_IDLE_EN	`RW`	`0x0`
1	`FPGA2SDRAM0_IDLEACK_EN`	FlagIn Enable register #1.FPGA2SDRAM0_IDLEACK_EN	`RW`	`0x0`
0	`FPGA2SDRAM0_IDLE_EN`	FlagIn Enable register #0.FPGA2SDRAM0_IDLE_EN	`RW`	`0x0`