MainPll_grp Address Map

Contains registers with settings for the Main PLL.
Module Instance Base Address End Address
i_clk_mgr_mainpllgrp 0xFFD10030 0xFFD1009F
Register Offset Width Access Reset Value Description
en 0x0 32 RW 0x000000FF 
Enable Register
ens 0x4 32 RW 0x000000FF 
Enable Set Register
enr 0x8 32 RW 0x000000FF 
Enable Reset Register
bypass 0xC 32 RW 0x0000003F 
Bypass Register
bypasss 0x10 32 RW 0x0000003F 
Bypass Set Register
bypassr 0x14 32 RW 0x0000003F 
Bypass Reset Register
mpuclk 0x18 32 RW 0x00000000 
Main PLL Control Register for MPU Clock Group.
nocclk 0x1C 32 RW 0x00000000 
Main PLL Control Register for NOC Clock Group.
cntr2clk 0x20 32 RW 0x00000001 
Main PLL Control Register for Counter 2 Clock
cntr3clk 0x24 32 RW 0x00000001 
Main PLL Control Register for Counter 3 Clock
cntr4clk 0x28 32 RW 0x00000003 
Main PLL Control Register for Counter 4 Clock
cntr5clk 0x2C 32 RW 0x00000001 
Main PLL Control Register for Counter 5 Clock
cntr6clk 0x30 32 RW 0x00000001 
Main PLL Control Register for Counter 6 Clock
cntr7clk 0x34 32 RW 0x00010000 
Main PLL Control Register for Counter 7 Clock
cntr8clk 0x38 32 RW 0x00000000 
Main PLL Control Register for Counter 8 Clock
cntr9clk 0x3C 32 RW 0x00000000 
Main PLL Control Register for Counter 10 Clock
nocdiv 0x40 32 RW 0x18020100 
NoC Divide Register
pllglob 0x44 32 RW 0x00000100 
This refects register settings for both the channels of the main PLL
fdbck 0x48 32 RW 0x2A000000 
VCO freq register counters
mem 0x4C 32 RW 0x00000000 
Registers dealing with PLL internal memory access.
memstat 0x50 32 RW 0x00000000 
Periph PLL memstatus register. contains ack and memory read data
pllc0 0x54 32 RW 0x08000002 
Channel C0 frequency settings for the main PLL
pllc1 0x58 32 RW 0x01000006 
Channel C1 settings for the main PLL
vcocalib 0x5C 32 RW 0x000009B7 
VCO calibration control registers.