pllglob

         This refects register settings for both the channels of the main PLL

Module Instance	Base Address	Register Address
`i_clk_mgr_mainpllgrp`	`0xFFD10030`	`0xFFD10074`

Size: 32

Offset: 0x44

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`														`psrc` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`refclkdiv` `RW 0x1`						`Reserved`			`bysctl` `RW 0x0`	`modsel` `RW 0x0`	`mute` `RW 0x0`	`rst` `RW 0x0`	`pd` `RW 0x0`

pllglob Fields

Bit

Name

Description

Access

Reset

17:16

psrc

Controls the VCO input clock source.

Value	Description
0	eosc1_clk
1	cb_intosc_clk
2	f2s_free_clk

RW

0x0

13:8

refclkdiv

Reference Clock Divider Control Registers; 
Fref_eff    = (Fref)/(refdiv[5:0])
Frq_mul = {(6+ mdiv[7:0]* (fdiv[23:0]/ (2^24)))}
Fsyn = Frq_mul * Fref_eff    
(Fsyn /6) >= 3* Fref_eff    

Fock_vpll_pr1   =    Fsyn /(pr1[7:0])

RW

0x1

bysctl

This bit is resposible for selecting source for bypass clock in PLL bypass mode. In the current version of the PLL. this feature is not supported.
Therefore it can be '0' or '1'. The value does not matter at all. 
Making it '0' by defaut

RW

0x0

modsel

terger mode, feedback divident to PLL is considered integer. It can be only set while the PLL is at reset or power down state. It cannot be switched dynamically.
Select: 1’B1 - Fractional Mode 
1’B0 - Integer Mode;

Value	Description
0	INT
1	FLOAT

RW

0x0

mute

Mutes All Pll Outputs Glitch-Free: 
1 – Output Clocks Are Muted To 1’B0; 
0 – Output Clocks Are Active

Value	Description
0	UNMUTE
1	MUTE

RW

0x0

rst

Pll Reset. Used to power down and initialize the synthesizer. Must be asserted when power supply pins are applied. 
1- Hard Reset Is De-Asserted; 
0-Hard Reset Is Asserted. 

This is an active low signal.
By default the signal is asserted. Software should come and write '1' in this reg to bring up the PLL

RW

0x0

pd

Pll Disable/Power-Down Control. This is an active low signal
1: Pll Analog circuits are Enabled; 
0: Pll is Disabled. 

By default the signal is asserted. Software should come and write '1' in this reg to bring up the PLL

Value	Description
0	POWERDOWN
1	POWERUP

RW

0x0