ddr_scheduler_fpga2sdram_manager_main_SidebandManager Summary

Base Address: 0xF8024000

Register Address Offset	Bit Fields
`soc_ddr_scheduler_inst_0_fpga2sdram_manager_main_SidebandManager`
`fpga2sdram_manager_main_SidebandManager_Id_CoreId` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CORECHECKSUM` `RO 0x9885CB`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CORECHECKSUM` `RO 0x9885CB`								`CORETYPEID` `RO 0xB`
`fpga2sdram_manager_main_SidebandManager_Id_RevisionId` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FLEXNOCID` `RO 0x148`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FLEXNOCID` `RO 0x148`								`USERID` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FaultEn` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`FAULTEN` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FaultStatus` `0xC` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`FAULTSTATUS` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagInEn0` `0x10` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`FPGA2SDRAM2_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM2_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM2_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM2_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM1_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM1_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_RESP_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_CMD_IDLE_EN` `RW 0x0`	`FPGA2SDRAM0_IDLEACK_EN` `RW 0x0`	`FPGA2SDRAM0_IDLE_EN` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagInStatus0` `0x14` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`				`FPGA2SDRAM2_RESP_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM2_CMD_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM2_IDLEACK_STATUS` `RO 0x0`	`FPGA2SDRAM2_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM1_RESP_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM1_CMD_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM1_IDLEACK_STATUS` `RO 0x0`	`FPGA2SDRAM1_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM0_RESP_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM0_CMD_IDLE_STATUS` `RO 0x0`	`FPGA2SDRAM0_IDLEACK_STATUS` `RO 0x0`	`FPGA2SDRAM0_IDLE_STATUS` `RO 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutSet0` `0x50` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`FPGA2SDRAM2_FORCE_DRAIN_SET` `RW 0x0`	`FPGA2SDRAM2_ENABLE_SET` `RW 0x0`	`FPGA2SDRAM2_IDLEREQ_SET` `RW 0x0`	`FPGA2SDRAM1_FORCE_DRAIN_SET` `RW 0x0`	`FPGA2SDRAM1_ENABLE_SET` `RW 0x0`	`FPGA2SDRAM1_IDLEREQ_SET` `RW 0x0`	`FPGA2SDRAM0_FORCE_DRAIN_SET` `RW 0x0`	`FPGA2SDRAM0_ENABLE_SET` `RW 0x0`	`FPGA2SDRAM0_IDLEREQ_SET` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutClr0` `0x54` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`FPGA2SDRAM2_FORCE_DRAIN_CLR` `RW 0x0`	`FPGA2SDRAM2_ENABLE_CLR` `RW 0x0`	`FPGA2SDRAM2_IDLEREQ_CLR` `RW 0x0`	`FPGA2SDRAM1_FORCE_DRAIN_CLR` `RW 0x0`	`FPGA2SDRAM1_ENABLE_CLR` `RW 0x0`	`FPGA2SDRAM1_IDLEREQ_CLR` `RW 0x0`	`FPGA2SDRAM0_FORCE_DRAIN_CLR` `RW 0x0`	`FPGA2SDRAM0_ENABLE_CLR` `RW 0x0`	`FPGA2SDRAM0_IDLEREQ_CLR` `RW 0x0`
`fpga2sdram_manager_main_SidebandManager_FlagOutStatus0` `0x58` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`FPGA2SDRAM2_FORCE_DRAIN_STATUS` `RO 0x0`	`FPGA2SDRAM2_ENABLE_STATUS` `RO 0x0`	`FPGA2SDRAM2_IDLEREQ_STATUS` `RO 0x0`	`FPGA2SDRAM1_FORCE_DRAIN_STATUS` `RO 0x0`	`FPGA2SDRAM1_ENABLE_STATUS` `RO 0x0`	`FPGA2SDRAM1_IDLEREQ_STATUS` `RO 0x0`	`FPGA2SDRAM0_FORCE_DRAIN_STATUS` `RO 0x0`	`FPGA2SDRAM0_ENABLE_STATUS` `RO 0x0`	`FPGA2SDRAM0_IDLEREQ_STATUS` `RO 0x0`